LMK04808BEVAL: PLL2 will not lock

Doug Bailey

Part Number: LMK04808BEVAL
Other Parts Discussed in Thread: LMK04808

I've run into another situation of tuning the second PLL on a LMK evaluation board. (I ran into somehting similar on a LMK04816B board.)

This is a LMK04808 eval board. I have switched out the VCXO from 122.88 MHz to 50 MHz using the same family of VCXO as the one originally on the eval board. I am trying to get the second PLL to lock at 3,000 MHz so that I can derive 375 MHz, 150 MHz, and 6.25 MHz.

I am running the part in Dual PLL mode.

I drive a 50 MHz signal in on CLKIn1. I see the first PLL lock via the DLD lock indicator.

I then have tried a number of settings for PLL2 to get it to lock at 3,000 MHz. Unfortunately, I do not see the DLD light for PLL2 and the VPTune2 test point is either at Gnd or pegged to the 3.3V rail.

When I measure PLL2 R/2, I see it track the phase detector frequency. The same is not true for PLL2 N/2 as it never locks onto the phase detector frequency.

I have tried a number of variations for setting the PLL dividers and phase detector frequencies. Most of these choices I have tried have been relatively random. Is there a more programmatic way of setting these values?

What should I be looking at in order to get the second PLL to lock?

Thanks

Doug Bailey

over 6 years ago

0 Derek Payne over 6 years ago

TI__Mastermind 34840 points

Hi Doug,

First quick check: is the PLL2 phase detector polarity set to negative?

Next: When you measure PLL2 R/2 and PLL2 N/2, is N/2 higher or lower frequency than R/2? Can you adjust the Pre-N-Divider and the N-Divider values until you find a range where the VCO does lock? I would start by setting the phase detector a frequency that has VCO divide values available above and below the target value. For example, with a phase detector frequency of 50 MHz, normally VCO divide should total to 60 (2 * 30); however, if the N/2 frequency is larger than the R/2 frequency, you could try setting the VCO divide value to 62 instead (2 * 31). And if it's lower, you could try setting the value to 58 (2 * 29). If the PLL manages to lock with a divide value other than the desired value, it could indicate an issue with VCO frequency calibration.

Let me know what you observe, and we can continue the debugging process.

Regards,

0 Doug Bailey over 6 years ago in reply to Derek Payne

Intellectual 290 points

Thanks for the information. It has been very helpful.

I did make sure that the polarity of the phase detector was negative.

I measured the PLL2 N/2 with a scope probe. I set my phase detector frequency to some values by adjusting PLL2 R so that I got values of 50, 40, 33.33 MHz.

I then adjusted the PLL2 N Pre N divider and PLL2 N divider to move the frequency of that signal closer to the phase detector frequency. I was able to get a lock on PLL2 but at a VCO frequency of 3200 MHz. (I assumed lock when the PLL2 DLD LED went active.)

This occurred with:

Phase Detector: 40 MHz

PLL2 N Pre Divider = 2, PLL2 N Divider 40

PLL2 R Multiplier 2, PLL2 R Divider = 5

Unfortunately, 3200 MHz VCO is outside of the part's operating range. I was unable to get it to lock at 3000 MHz.

My next step is to adjust the PLL2 tuning circuit. I am currently using the default tuning circuit that comes with the board. I ran the Clock Design Tool and it suggested new values for the tuning circuit. These are:

Component Default New

C1: 47 pF 27 pF

C2: .0039 uF .0027 uF

R2: 620 ohm 680 ohm

I will get my board modified to set these new values and try again to get it to lock at 3000 MHz.

Doug

0 Doug Bailey over 6 years ago in reply to Doug Bailey

Intellectual 290 points

After changing the PLL2 Loop filter, I was able to get the device to lock at a PLL2 VCO of 3000 MHz.

I ended up using the following PLL2 settings:

R Multiplier: 2
R Divisor: 4
Pre N Divisor: 5
N Divisor: 12
Phase Detector: Negative Polarity, 50 MHz, 3.2 mA

This is with a 100 MHz VCXO and a Loop filter components:

R2: 680 ohm
R3: 200 ohm
R4: 200 ohm
C1: 27 pF
C2: .0027 uF
C3: 10 pF
C4: 10 pF

The device seemed to lock better at 3200 MHz but I did eventually find settings for 3000 MHz.

Thanks for your assistance.

Clock & timing

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LMK04808BEVAL: PLL2 will not lock