LMK04832: Clock gate options

user6150486

Part Number: LMK04832

Hi,

I would like to use the part for my system and I have some question regarding clock gating of the output

I've a sensitive system that should get 100MHz clock on startup and then move into a 300MHz clock without creating a glitch.

in between the clock changes I would like to stop the clock and be sure that OE of the clock out will be clean (clock gate) and not only powered down the clock.

sequence:

power on LMK and set it to 100MHz, run for some time (<few seconds)

stop the clock - should be clean and clock gated

power on the clock LMK back in 300MHz

please let me know if the device support such a clock gating configuration

Thanks,

Asaf

over 6 years ago

0 Derek Payne over 6 years ago

TI__Mastermind 33430 points

Hello Asaf,

If I understand correctly, you want a transition between two output frequencies that does not truncate any pulses. It also sounds like some delay is allowed during the transition where the clock is to be held in some state (low) until the frequency change is completed. This is possible to do with the LMK04832 using the SYSREF_REQ_EN setting.

Program the PLL normally, using the SYSREF divider and SCLK output paths to generate the 100 MHz: SCLKx_y_PD = 0, CLKout_SRC_MUX = 1
Enable SYSREF: SYNC_EN = 1, SYNC_DISSYSREF and SYNC_DISx = 1, SYSREF_PLSR_PD = 0, SYSREF_MUX != 3, SYSREF_REQ_EN = 1
To generate output clocks, either toggle the SYNC pin manually, or toggle in software using SYNC_POL=1
To change clocks, deassert SYNC pin or return SYNC_POL=0. Then, reconfigure the divider to output 300 MHz and return to step 3

The SYSREF_REQ output enable is gated to ensure complete cycles, so this should satisfy the clean stop requirement.

Regards,

0 user6150486 over 6 years ago in reply to Derek Payne

Prodigy 20 points

Thanks. i got the answer for my question

Clock & timing

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LMK04832: Clock gate options