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LMK04208: JESD204B Compliant devices

Max Pom
Intellectual 350 points
Part Number: LMK04208
Other Parts Discussed in Thread: LMK04828, , LMX2594, LMK04832

Hello,

I need to design a clock tree to support the Xilinx RFSoC, and I have a few questions about Clock distribution devices supporting JESD204B.

- What makes a device to be JESD204B compliant?

If I understood correctly, it suppose to generate both the high speed (clean) clock to be the sampling clock of a data converter,

and the SYSREF clock, which is a lower frequency but with the same phase (Sampling clock divided by certain factor) + capabele of phase alignment to compensate PCB traces.

- Why the LMK04208  has not been declared as JESD204B compliant? (how it differs from LMK04828 for instance?)

- If I use a non JESD204B compliant device to generate both the SYSREF, and a Reference clock for other (high frequency) PLL which generates the Sampling clock, will I comply the JESD204B?

 I saw a design (Xilinx RFSoC Eval board - ZCU111, https://www.xilinx.com/products/boards-and-kits/zcu111.html)

which uses the LMK04208 to generate the SYSREF Clocks for the RFSoC, and the Ref.+Sync. Clocks for the LMX2594 to be the Sampling clocks.

- When do I need to assert the SYNC input to a device, to ensure that the output phase of all clocks is the same?

In the same example (Xilinx RFSoC Eval board - ZCU111), The SYNC to the LMX2594 is not asserted.

- The High frequency Sampling clock for the  data converter must be clean, to not degrade the performance (SNR etc.). Does the SYSREF also influence the performane and must be clean as well?

  • 0
    TI__Mastermind 28550 points

    Hello Max,

    Max Pom said:
    - What makes a device to be JESD204B compliant?


    JESD204B is primarily a spec for the data interface between logic devices like FPGA and data converters.]

    From a clocking perspective "JESD204B support" is as simple provide a low frequency clock (or pulse) along with the high frequency clock as you later state.  However there are details which can be made similar with a device intended for JESD204B.

    Max Pom said:
    - Why the LMK04208  has not been declared as JESD204B compliant? (how it differs from LMK04828 for instance?)

    It was not designed intended for JESD204B, although it could work in such a role as it...

    • Has reasonably large dividers
    • Supports digital and analog phase adjustment of clocks with respect to each other (so you can achieve the desired setup and hold time).

    The LMK0482x and LMK04832...

    • support a single SYSREF divider that is able to divide by values up to 8191 for those low SYSREF frequencies.  This can help reduce power as only a single divider is running for all SYSREF outputs.
    • support the ability to generate a clean 1, 2, 4, or 8 pulses for SYSREF upon pin or SPI request.
    • support the ability to provide SYSREF continuously upon assertion of external SYNC pin operating as SYSREF request.
    • support the ability to re-clock an input sync/sysref signal through CLKin0 to reset dividers on device, or to pass this through to downstream devices.  This feature is key to help achieve synchronization of multiple clocking devices providing SYSREF to multiple JESD204B targets to receive a SYSREF at the exact same moment.
    • Support LCPECL, an output format with relatively low common mode voltage with high swing that allows resistive division of the clock to a lower common mode voltage.  This is important if you want to DC couple to converters with lower voltage rails which require common mode voltages on the clock of 0.5 V for example.
      • AC coupling is also an option, this has advantages (no concern for DC level) and disadvantages (more complicated, longer to achieve synchronization)

    Probably a bit more to say, but that gives you an idea.

    Max Pom said:
    - If I use a non JESD204B compliant device to generate both the SYSREF, and a Reference clock for other (high frequency) PLL which generates the Sampling clock, will I comply the JESD204B?

    You can.  I recommend the device at a minimum have the ability to adjust phase with respect to other clocks.

    Max Pom said:
    - When do I need to assert the SYNC input to a device, to ensure that the output phase of all clocks is the same?

    Typically at power up you will assert SYNC pin (or toggle a software invert on the SYNC pin to achieve SYNC by software).  This gives all clocks deterministic phase as per offsets programmed into digital delay.

    Note on LMK04828, the SYNC/SYSREF path is shared, so you would SYNC all the dividers, then re-configure for SYSREF output by disabling the ability of the dividers to be synchronized.

    Max Pom said:
    - The High frequency Sampling clock for the  data converter must be clean, to not degrade the performance (SNR etc.). Does the SYSREF also influence the performane and must be clean as well?

    If SYSREF is running continuously, then it has some risk for crosstalk impacting the data converter clock.  That is why SYSREF clocks are typically powered down after synchronizing the system, it saves power too.

    How can SYSREF clock performance impact SYSREF?  Its jitter could impact it's placement to setup and hold of input clocks of other devices, but this is typically insignificant.  Suppose it has a jitter of 200 fs rms.  If you consider a BER of 1:10^12 would multiply 200 fs rms --> 2.8 ps pk-pk.  2.8 ps is a small contributor to overall setup and hold time with 1 error in 10^12 edges.

    -

    Bottom line is, the lower the frequency of your device clocks, the more flexibility you have with how you generate SYSREF.  However for high speed clocks, over say 2 GHz, the timing for placement of the SYSREF in the device clock becomes more tricky and less forgiving if you want +/- 0 device clock error.

    Hope this helps.

    73,
    Timothy