I'm using an LMK04832 in "Single-Loop" Mode [I'm "Only" using PLL2] for my JESD Application [Analog Devices AD9695 + Xilinx ZU9EG].
I'm running the JESD in Sub Class-0 Mode for my "Short" Term Demo and I will be running the JESD in Sub Class-1 Mode for my "Long" Term Application.
A). Sub Class-0 Operation
1. Reference is 100MHz Input to CLKin1
a. CLKin1 Type = MOS
b. CLKin1 Enable = 1
2. CLKin0 and CLKin2 "Not" used
a. CLKin0 Type = Bipolar
b. CLKin0 Enable = 0
c. CLKin2 Type = Bipolar
d. CLKin2 Enable = 0
2. VCO1 is Running at 3200MHz
3. SDCLK1 = 320MHz, DCLK8 = 640MHz
4. No SYSREF Generation in LMK04832
5. Output Clock Dividers are "Synchronized" via SYNC/SYSREF Pin
6. Status_LD1 Pin = PLL2_DLD
7. I program the LMK using the Following Sequence
A. LMK Class-0 Configuration
// Reset SPI, Disable 3-Wire SPI Mode
Write 0x0000 0x90; Reset SPI [Self Clears in 120ns], Disable 3-Wire SPI Mode
Write 0x0000 0x10; SPI Out of Reset, Disable 3-Wire SPI Mode
// Use Reset/GPO Pin as SPI Readback
Write 0x014A, 0x33; RESET_TYPE = Output [Push/Pull], RESET_MUX = SPI Readback
// Clock Group 1 (DCLK0 = Powered Down, SDCLK1 = 640MHz_REF); Note: SDCLK1 "Changed" to 320MHz for Serdes Reference
Write 0x0100, 0x0A; DCLK0_1_DIV = 10 [3200MHz/10 = 320MHz_SYS]
Write 0x0101, 0x08; DCLK0_1_DDLY = 8
Write 0x0102, 0x00; CLK0_1_PD = 0, ODL = 0, IDL = 0, DDLY0_1_PD = 0, DDLY[9:8] = 0, DIV[9:8] = 0
Write 0x0103, 0x44; DCLK0_1_HS = 0, DCLK0_1_POL = 0, DCLK0_1_DCC = 1, DCLK0_BYP = 0, CLKout0_1_PD = 0, CLKout0_SRC_MUX = 0 {Device}, DCLK0_1_HSg_PD = 1
Write 0x0104, 0x00; SCLK0_1_HS = 0, SCLK0_1_POL = 0, SCLK0_1_DIS_MODE = 0, SCLK0_1_PD = 0, CLKout1_SRC_MUX = 0 [Device]
Write 0x0105, 0x00; No Analog Delay, Disable Analog Delay
Write 0x0106, 0x00; SCLK0_1_DDLY = 0
Write 0x0107, 0x40; SDCLK1 = LVPECL16, DCLK0 = Powered Down
// Clock Group 2 (DCLK2 = 160MHz_DAC, SDCLK3 = DAC_SYSREF); Note: DCLK2/SDCLK3 "Changed" to Powered Down [No DAC Usage]
Write 0x0108, 0x14; DCLK2_3_DIV = 20 [3200MHz/20 = 160MHz_DAC]
Write 0x0109, 0x08; DCLK2_3_DDLY = 8
Write 0x010A, 0x80; CLK2_3_PD = 1, ODL = 0, IDL = 0, DDL2_3_PD = 0, DDL[9:8] = 0, DIV[9:8] = 0
Write 0x010B, 0x54; DCLK2_3_HS = 0, DCLK2_3_POL = 0, DCLK2_3_DCC = 1, DCLK2_BYP = 0, CLKout2_3_PD = 1, CLKout2_SRC_MUX = 0 {Device}, DCLK2_3_HSg_PD = 1
Write 0x010C, 0x24; SCLK2_3_HS = 0, SCLK2_3_POL = 0, SCLK2_3_DIS_MODE = 1, SCLK0_1_PD = 0, CLKout3_SRC_MUX = 1 [SYSREF]
Write 0x010D, 0x00; No Analog Delay, Disable Analog Delay
Write 0x010E, 0x00; SCLK2_3_DDLY = 0
Write 0x010F, 0x00; SDCLK3 = Powered Down, DCLK2 = Powered Down
// Clock Group 3 (DCLK4 = Powered Down, SDCLK5 = ADC1_SYSREF)
Write 0x0110, 0x0A; DCLK4_5_DIV = 10 [3200MHz/10 = 320MHz; Not Used]
Write 0x0111, 0x08; DCLK4_5_DDLY = 8
Write 0x0112, 0x00; CLK4_5_PD = 0, ODL = 0, IDL = 0, DDL4_5_PD = 0, DDL[9:8] = 0, DIV[9:8] = 0
Write 0x0113, 0x54; DCLK4_5_HS = 0, DCLK4_5_POL = 0, DCLK4_5_DCC = 1, DCLK4_BYP = 0, CLKout4_5_PD = 1, CLKout2_SRC_MUX = 0 {Device}, DCLK4_5_HSg_PD = 1
Write 0x0114, 0x24; SCLK4_5_HS = 0, SCLK4_5_POL = 0, SCLK4_5_DIS_MODE = 1, SCLK4_5_PD = 0, CLKout5_SRC_MUX = 1 [SYSREF]
Write 0x0115, 0x00; No Analog Delay, Disable Analog Delay
Write 0x0116, 0x00; SCLK4_5_DDLY = 0
Write 0x0117, 0x40; SDCLK5 = LVPECL16, DCLK4 = Powered Down
// Clock Group 4 (DCLK6 = Powered Down, SDCLK7 = ADC2_SYSREF)
Write 0x0118, 0x0A; DCLK6_7_DIV = 10 [3200MHz/10 = 320MHz; Not Used]
Write 0x0119, 0x08; DCLK6_7_DDLY = 8
Write 0x011A, 0x00; CLK6_7_PD = 0, ODL = 0, IDL = 0, DDL6_7_PD = 0, DDL[9:8] = 0, DIV[9:8] = 0
Write 0x011B, 0x54; DCLK6_7_HS = 0, DCLK6_7_POL = 0, DCLK6_7_DCC = 1, DCLK6_BYP = 0, CLKout6_7_PD = 1, CLKout6_SRC_MUX = 0 {Device}, DCLK6_7_HSg_PD = 1
Write 0x011C, 0x24; SCLK6_7_HS = 0, SCLK6_7_POL = 0, SCLK6_7_DIS_MODE = 1, SCLK6_7_PD = 0, CLKout7_SRC_MUX = 1 [SYSREF]
Write 0x011D, 0x00; No Analog Delay, Disable Analog Delay
Write 0x011E, 0x00; SCLK6_7_DDLY = 0
Write 0x011F, 0x40; SDCLK7 = LVPECL16, DCLK6 = Powered Down
// Clock Group 5 (DCLK8 = 320MHz_FPGA_Core1, SDCLK9 = FPGA_Core1_SYSREF); Note: DCLK8 "Changed" to 640MHz for DSP Engine Clock
Write 0x0120, 0x05; DCLK8_9_DIV = 10 [3200MHz/5 = 320MHz_FPGA_Core1; ADC1]
Write 0x0121, 0x08; DCLK8_9_DDLY = 8
Write 0x0122, 0x00; CLK8_9_PD = 0, ODL = 0, IDL = 0, DDL8_9_PD = 0, DDL[9:8] = 0, DIV[9:8] = 0
Write 0x0123, 0x44; DCLK8_9_HS = 0, DCLK8_9_POL = 0, DCLK8_9_DCC = 1, DCLK8_BYP = 0, CLKout8_9_PD = 0, CLKout8_SRC_MUX = 0 {Device}, DCLK8_9_HSg_PD = 1
Write 0x0124, 0x24; SCLK8_9_HS = 0, SCLK8_9_POL = 0, SCLK8_9_DIS_MODE = 1, SCLK6_7_PD = 0, CLKout9_SRC_MUX = 1 [SYSREF]
Write 0x0125, 0x00; No Analog Delay, Disable Analog Delay
Write 0x0126, 0x00; SCLK8_9_DDLY = 0
Write 0x0127, 0x11; SDCLK9 = LVDS, DCLK8 = LVDS
// Clock Group 6 (DCLK10 = 320MHz_FPGA_Core2, SDCLK11 = FPGA_Core2_SYSREF); Note: DCLK10 "Changed" to Powered Down
Write 0x0128, 0x0A; DCLK10_11_DIV = 10 [3200MHz/10 = 320MHz_FPGA_Core2; ADC2]
Write 0x0129, 0x08; DCLK10_11_DDLY = 8
Write 0x012A, 0x00; CLK10_11_PD = 0, ODL = 0, IDL = 0, DDL10_11_PD = 0, DDL[9:8] = 0, DIV[9:8] = 0
Write 0x012B, 0x54; DCLK10_11_HS = 0, DCLK10_11_POL = 0, DCLK10_11_DCC = 1, DCLK10_BYP = 0, CLKout10_11_PD = 1, CLKout10_SRC_MUX = 0 {Device}, DCLK10_11_HSg_PD = 1
Write 0x012C, 0x24; SCLK10_11_HS = 0, SCLK10_11_POL = 0, SCLK10_11_DIS_MODE = 1, SCLK10_11_PD = 0, CLKout11_SRC_MUX = 1 [SYSREF]
Write 0x012D, 0x00; No Analog Delay, Disable Analog Delay
Write 0x012E, 0x00; SCLK10_11_DDLY = 0
Write 0x012F, 0x10; SDCLK11 = LVDS, DCLK10 = Powered Down
// Clock Group 7 (DCLK12 = 320MHz_FPGA_Core3, SDCLK13 = FPGA_Core3_SYSREF); Note: DCLK12/SDCLK13 "Changed" to Powered Down [No DAC Usage]
Write 0x0130, 0x0A; DCLK12_13_DIV = 10 [3200MHz/10 = 320MHz_FPGA_Core3; DAC]
Write 0x0131, 0x08; DCLK12_13_DDLY = 8
Write 0x0132, 0x80; CLK12_13_PD = 1, ODL = 0, IDL = 0, DDL12_13_PD = 0, DDL[9:8] = 0, DIV[9:8] = 0
Write 0x0133, 0x54; DCLK12_13_HS = 0, DCLK12_13_POL = 0, DCLK12_13_DCC = 1, DCLK12_BYP = 0, CLKout12_13_PD = 1, CLKout12_SRC_MUX = 0 {Device}, DCLK12_13_HSg_PD = 1
Write 0x0134, 0x24; SCLK12_13_HS = 0, SCLK12_13_POL = 0, SCLK12_13_DIS_MODE = 1, SCLK12_13_PD = 0, CLKout13_SRC_MUX = 1 [SYSREF]
Write 0x0135, 0x00; No Analog Delay, Disable Analog Delay
Write 0x0136, 0x00; SDCLK12_13_DDLY = 0
Write 0x0137, 0x00; SDCLK13 = Powered Down, DCLK12 = Powered Down
// SYSREF, SYNC, and Device Config
Write 0x0138, 0x20; OSCOut = Powered Down, OSCOut_MUX = Buffered OSC_IN, VCO_MUX = VCO1 [2945MHz to 3255MHz]
Write 0x0139, 0x00; SYSREF_MUX = Normal, SYNC_BYPASS = Normal, SYSREF_REQ_EN = Disabled, SYSREF_TEMP_COMP = Disabled
Write 0x013A, 0x00; SYSREF_DIV = 32 [3200MHz/32 = 100MHz]
Write 0x013B, 0x20
Write 0x013C, 0x00; SYSREF_DDLY (GBL) = 8
Write 0x013D, 0x08
Write 0x013E, 0x00; (1) SYSREF Pulse
Write 0x013F, 0xA5; FB_MUX_EN = 1, FB_MUX = SYSREF_DIV, PLL1_NCLK_MUX = OSCin [Not Used], PLL2_NCLK_MUX = FB_MUX, PLL2_RCLK_MUX = Selected CLKin [CLKIN1]
Write 0x0140, 0x99; SYSREF_PLSR_PD = 1, SYSREF_DDLY_PD = 0, SYSREF_PD = 0, SYSREF_GBL_PD = 1, OSCin_PD = 1, VCO_PD = 0, VCO_LDO_PD = 0, PLL1_PD = 1
Write 0x0141, 0x00; Disable Dynamic Digital Delay for DCLK0, DCLK2, DCLK4, DCLK6, DCLK8, DCLK10, DCLK12, and SYSREF
Write 0x0142, 0x00; DDLYd_STEP_CNT = 0
Write 0x0143, 0x91; SYSREF_CLR = 1, SYNC_POL = Normal, SYNC_EN = 1, SYNC_MODE = SYNC Pin
Write 0x0144, 0x80; Enable SYNC Event for "All" DCLKout Divider, Disable SYNC Event for SYSREF Divider
Write 0x0145, 0x00; PLL2R_SYNC_EN = 0, PLL1R_SYNC_SRC = Reserved, PLL1R_SYNC_EN = 0
// CLKin Control
Write 0x0146, 0x12; CLKin0_EN = 0, CLKin1_EN = 1, CLKin2_EN = 0, CLKin1 = MOS [For LOS Measure], CLKin0 = CLKin2 = Bipolar [Differential]
Write 0x0147, 0x1B; CLKin0_OUT_MUX = Off, CLKin1_OUT_MUX = PLL1, CLKin_SEL_MANUAL = CLKin1
Write 0x0148, 0x00; CLKin_SEL0_TYPE = Input
Write 0x0149, 0x00; CLKin_SEL1_TYPE = Input
Write 0x014A, 0x33; RESET_TYPE = Output [Push/Pull], RESET_MUX = SPI Readback
// Hold Over
Write 0x014B, 0x26; LOS_EN = 1, Man_DAC[9:0] = 512
Write 0x014C, 0x00
Write 0x014D, 0x00; DAC_TRIP_LOW = 0
Write 0x014E, 0xC0; DAC_TRIP_HIGH = 0, DAC_CLK_MULT = 16,384
Write 0x014F, 0x7F; DAC_CLK_CNTR = 127
Write 0x0150, 0x00; NO CLKin Override??? [Synthesizer Mode]
Write 0x0151, 0x02; HOLDOVER_DLD_CNT =
Write 0x0152, 0x00
// PLL1 Configuration
Write 0x0153, 0x00; CLKin0_R = 120 [PLL1 "Not" Used; Powered Down]
Write 0x0154, 0x78
Write 0x0155, 0x00; CLKin1_R = 1 [PLL2 "Used"; CLKin1 = 100MHz]
Write 0x0156, 0x01
Write 0x0157, 0x00; CLKin2_R = 120 [CLKin2 "Not" Used]
Write 0x0158, 0x78
Write 0x0159, 0x00; PLL1_N = 1 [PLL1 "Not" Used; Powered Down]
Write 0x015A, 0x01
Write 0x015B, 0xD4; PLL1_WND_SIZE = 43ns, PLL1_CP_GAIN = 450uA [PLL1 "Not" Used; Powered Down]
Write 0x015C, 0x20; PLL1_DLD_CNT = 8192
Write 0x015D, 0x00
Write 0x015E, 0x1E; HOLDOVER_EXIT_NADJ = 30
Write 0x015F, 0x03; PLL1 LD Pin = Output (Push-Pull), Logic "Low"
// PLL2 Configuration
Write 0x0160, 0x00; PLL2_R = 1 [PLL2 "Used"; PFD = 100MHz]
Write 0x0161, 0x01
Write 0x0162, 0x24; PLL2_P = 2 [Pre-Scaler] 63MHz < OSCin_FREQ < 127MHz [OSCin "Not" Used]
Write 0x0163, 0x00; PLL2_N Cal Divider = 16 [(3200MHz/2/16) = 100MHz]
Write 0x0164, 0x00
Write 0x0165, 0x10
Write 0x0173, 0x10; PLL2_PRE_PD = 0 [PLL2 PreScaler "Used"], PLL2_PD = 0 [PLL2 "Used"]
Write 0x0166, 0x00; PLL2_N = 1
Write 0x0167, 0x00
Write 0x0168, 0x01
Write 0x0169, 0x79; PLL2_WND_SIZE = 2.6ns [When PFD < 160MHz], PLL2_CP_GAIN = 3200uA, PLL2_DLD_EN = 1
Write 0x016A, 0x20; PLL2_DLD_CNT = 8192
Write 0x016B, 0x00
Write 0x016C, 0x00; "Fixed"; Use POR
Write 0x016D, 0x00; "Fixed"; Use POR
Write 0x016E, 0x13; PLL2 LD Pin = Output (Push-Pull), PLL2_LD
Write 0x0177, 0x00; PLL1_R_RST [Used to "Reset" PLL1_R]
Write 0x0182, 0x01; CLR PLL1_LD_LOST = 0, CLR PLL2_LD_LOST = 1
Write 0x182, 0x00; CLR_PLL1_LD_LOST = 0, CLR PLL2_LD_LOST = 0
Write 0x0555, 0x00; SPI Registers "Unlocked"
// Synchronize Output Clock Dividers
Write 0x143 0xB1 ; SYSREF_CLR = 1, SYNC_POL = Inverted, SYNC_EN = 1, SYNC_MODE = SYNC Pin
Write 0x143 0x91 ; SYSREF_CLR = 1, SYNC_POL = Normal, SYNC_EN = 1, SYNC_MODE = SYNC Pin
// Disable Output Clock Divider Synchronization
Write 0x0144, 0xFF; Disable SYNC Event for "All" DCLKout Divider, Disable SYNC Event for SYSREF Divider
7. After I program the Sequence, I then Check to see if the 100MHz is "Present" at CLKin1 Pin [Using RB_CLKin1_LOS]
// Verify 100MHz is Present
Read 0x0184; 100MHz is "Present" when 0x184[1] = 0
8. After I "Verify" that the 100MHz is "Present" at CLKin1 Pin, I then "Verify" that PLL2 is "Locked" to the 100MHz Reference [Using RB_PLL2_LD]
// Verify PLL2 is Locked
Read 0x0183; PLL2 "Locked" when 0x183[0] = 1
9. After I "Verify" that the 100MHz is "Present" at CLKin1 Pin, and "Verify" that PLL2 is "Locked" to the 100MHz Reference, I "Shut-Off" the 100MHz Reference Source
10. I then "Verify" that the 100MHz is "Not" Present at CLKin1 Pin [Using RB_CLKin1_LOS]
// Verify 100MHz is Not Present
Read 0x0184; 100MHz is "Not Present" when 0x184[1] = 1
Question-1: Register 0x184[1] will "Readback" a "1"...…."Only" if LOS_EN = 1...…..Is this Correct?
11. It appears to be Correct, based on the Data Sheet [See Below]:
12. I "Re--Apply" the 100MHz Reference Source to CLKin1 and then "Re-Verify" that the 100MHz is "Present" at CLKin1 Pin, and "Verify" that PLL2 is "Locked" to the 100MHz Reference
// Verify 100MHz is Present
Read 0x0184; 100MHz is "Present" when 0x184[1] = 0
// Verify PLL2 is Locked
Read 0x0183; PLL2 "Locked" when 0x183[0] = 1
12. I then connect Channel-1 of my to the Status_LD1 Pin [This Pin is configured to "Monitor" PLL2_LD]
13. At this point in time, Status_LD2 Pin = "High"; PLL2 is Locked
14. I then set the Scope to Trigger on the "Falling" Edge of Channel-1 and set the Time Base to 400ms/Div
15. I then send the "Entire" Programming Sequence...…"Again"...….to the LMK04832...….to "Monitor" PLL2 going "Out" of "Lock".....and then "Re-Acquiring" Lock
16. Once the Oscilloscope Triggers......I can see the Status_LD2 Pin go "Low"...…."Remain Low" for 1600ms...…..and then Transition "High"
17. I computed the PLL2 Lock time to be 8,192/100MHz as per the Data Sheet [See Below]:
Question-2: I computed the "Minimum" PLL2 Lock time to be 81.92uS, but on the Oscilloscope I see the PLL2_LD "low" for 1600ms...…."Why" did it take "So" Long to Lock.....by me "Simply" Sending the Programming Sequence to the LMK a 2nd Time?...…..is it due to the fact that a 2nd Calibration was required?
