CDCE62005: not generating required clock

Shahzad Raza

Part Number: CDCE62005
Other Parts Discussed in Thread: DAC34H84

I want to use DAC34H84 EVM at maximum 1.25 GSa/s through xilinx fmc adapter. I am using CDCE62005 for DACCLK generation. My current configuration for DACCLK is attached.
With my current configuration I am getting Y3:FPGACLK of around 384 MHz with divider value set to 2. When I set divider value to 1, the clock disappears.

I also tried changing loop filter values but no use.

What should be the CDCE62005 clock configuration to achieve maximum sampling rate of 1.25 GSa/s?

over 5 years ago

0 Noel Fung over 5 years ago

TI__Guru* 89200 points

Hi Shahzad,

This is the DAC's GUI, our team do not familiar with it. Suggest you make a post in the Data converters forum.

I will close this post and if you have questions on the CDCE device, feel free to make a new post here.

Clock & timing

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CDCE62005: not generating required clock