• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 23 subscribers
  • Views 1110 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

HSDS and LCPECL

LMK04832: Termination about LCPECL

diverger
Expert 1205 points
Part Number: LMK04832
Other Parts Discussed in Thread: ADC34J43, ADC34J43EVM

I'm designning a board based on lmk04832 and adc34j43, taking ADC34J43EVM as reference. And I feel the termination schema is like a black box, especially for LCPECL output. I can't find any doc about LCPECL, it seems it used only by TI??? The eval board use LCPECL for SYSREFCLK, use 7.5Ohm series resistor. How 7.5Ohm is get? Can TI provide some clues?  

  • 0
    TI__Guru* 90880 points

    Hi diverger,

    As long the clock signal is AC-coupled to the ADC, it does not matter what is the clock signal output format. (here assume the clock signal amplitude meets with the ADC input requirement).

    I will let my colleague to comment on the 7.5Ω series resistor.

  • 0 in reply to Noel Fung
    TI__Mastermind 30920 points

    Hi diverger,

    In this case, 7.5Ω is likely used as part of a voltage divider, to adjust the signal amplitude. LCPECL frequently uses the emitter resistor as a voltage divider to set the amplitude and common-mode voltage of the DC-coupled signal, see below:

    Regards,

  • 0 in reply to Derek Payne
    Expert 1205 points

    Yes, for matching to the receiver input, We need adjust the common mode voltage using R2, and the swing using R1. But in ADC34J43EVM, it use 0 Ohm for R2. So the Vcm at the receiver is only 0.5V (Icc = 20mA).  But the ADC is internally biased to 0.9V. So why it set the common mode voltage to 0.5V at the receiver but not 0.9V?

    Thanks.

  • 0 in reply to diverger
    TI__Mastermind 30920 points

    Now that I think about it, the equations above are probably no longer valid for the case where the two ends of the differential pair are separately terminated. So I suspect in the EVM case it has more to do with tuning impedance mismatch from the PECL driver.

    To be honest, I'm not sure. I will try to locate the EVM designer and ask about the termination.

    Regards,

  • 0 in reply to Derek Payne
    TI__Genius 12780 points

    Hi Diverger,

    Are you still in need of assistance with this issue? The implementation that is used on the ADC34J43EVM does work for evaluation purposes, but, to me and others, is not a very clear solution.

    My suggestion is to set the common mode (0.9VDC) and amplitude (around 1 Vpp is ok) , as my colleague Derek has shown, at the output of the LMK and don't worry about matching at the ADC input. Please do not attempt to carry out what the EVM is doing. If you need assistance with this process, we are happy to help.

    Best Regards,

    Dan