Hello.
I'm working on a clock generator based on LMK04832. Device spec is:
- dual loop mode with holdover enabled
- PLL1: CLKin1 with 10MHz input and 10MHz output
- PLL2: OSCin 10MHz input, using internal VCO1 with 3200MHz, and 400MHz output
When I'm trying to program required frrequency into register OSCin_FREQ nr 0x162 (value 0 for 0 to 63MHz freq. as stated in the datasheet) , the PLL2 is not locking. If i set default value - it's locking.
Is there any reason for such behavior?
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/48/TICSPro_5F00_PLLatinumSim_5F00_cfg.7z