Hi team,
My customer has designed a clock tree with LMK03328 and the input clock input will be PRIREF and SECREF both with PLL1.
They couldn't generate the normal clock output when they use 74.25MHz input at PRIREF and the situation will be Priref loss of signal = 0, PLL1 loss of lock = 1. But it operate normally at SECREF with 74.25MHz.
Whether there is any suggestion to converge the issue for my customer.
Please refer the below link for configuration and schematic.
https://txn.box.com/s/dckz3zkdaxehd2gqen1xt1krxhw37qgc
There are also few questions as below.
- Could you provide the LF cap C2 analog ground requirement or layout example? Is it signal sensitive pin or not?
- Customer has a pre-stage 4:1 MUX that it's power rail is 2.5V, LMK03328 weak bias Vbb 1.8V, any sequence requirement on the DC coupling mode for avoiding EOS.
-
The PLL will enter into latch situation when PLL couldn't be locked. If they change the input clock from primary to secondary, it couldn't work anymore except rebooting power.
Whether there is any way can reset the PLL without rebooting power
Thank for your help.
