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Original question:

The LVDS clock output from CDCI6214 is incorrect

CDCI6214: Distorted LVDS output signal

Guido Peulen
Prodigy 80 points
Part Number: CDCI6214
Other Parts Discussed in Thread: CDCE6214-Q1

Hi TI,

I have the CDCI6214 powered with a 3V3 voltage on all power pins (VDDREFm VDDVCO, VDDO12 and VDDO34) to achieve the correct levels on the outputs which have been configured for single ended CMOS use on Y2P. I want the Y1P and Y1N to be configured as a LVDS output.

However when I select the output standard for Y1P and Y1N to be LVDS and the VDDO12 voltage to be 2.5V/3.3V in the TICS pro tool, the resulting LVDS signal is distorted and full of jitter. The PLL, however, is locked.

When I select 1.8V for the VDDO12 voltage the output is correct and as expected. 

Because I am feeding the VDDO12 voltage with 3V3 I assume that this setting is wrong. Can you tell me if it is possible to generate a LVDS output signal with VDDO12 = 3V3?

best regards,

Guido

  • 0
    TI__Mastermind 18070 points

    Hello Guido,

    I'll look into this and get back to you soon.

    Regards,
    Hao

  • 0 in reply to Hao Z
    TI__Mastermind 18070 points

    Hi Guido,

    2.5V/3.3V should be selected for LVDS output if 3.3V supply is used. Choosing 1.8V may damage the part. I checked this on a phase noise analyzer as well as oscilloscope when 3.3V supply is used and 2.5V/3.3V is selected. Both phase noise and waveform are fine. Can you send me your tcs configuration (File -> Save). You can then zip the file because .tcs file cannot be uploaded.

    Regards,

    Hao

  • 0 in reply to Hao Z
    Prodigy 80 points

    Hi Hao,

    I have added a zip file with the requested .tcs file. I have also added two scope pictures with the LVDS Y1P signal measured at the output of the CDCI6214 device. The Y1P signal 3V3 setting picture displays the Y1P signal with the 3V3 setting in the TICS pro software. I see a common mode voltage of about 3.0 V. With the 1V8 setting (Y1P signal 1V8 setting picture) the common mode voltage is to be expected about 1.2V.

    best regards,

    Guido Peulen

    CDCI6214_LVDS_level_problem.zip

  • 0 in reply to Guido Peulen
    TI__Mastermind 18070 points

    Hi Guido,

    I may be wrong but looking at your waveform, it seems that it's not properly triggered? You may want to move down the trigger level a bit because the common mode is slightly lower. I still didn't see this kind of waveform on my end. Besides, I didn't find anything wrong in the register setting.

    Regards,

    Hao

  • 0 in reply to Hao Z
    Prodigy 80 points

    Hi Hao,

    Looking at the 3V3 waveform (y1p signal 3v3 setting.jpg), you see that the common mode voltage is about 3V and the Vpp is 100 mV. This cannot be right, I assume. According to the specification the common mode voltage should be 1V2 as is the case with the 1V8 setting (y1p signal 1v8 setting.jpg).

    Maybe the part has been damaged by using the wrong setting, but this would not explain why changing the 3V3/1V8 setting gives the correct output common mode voltage. 

    regards,

    Guido

  • 0 in reply to Guido Peulen
    TI__Mastermind 18070 points

    Hi Guido,

    I checked your scopeshots again and the amplitude at 3.3V is off. Normally the differential voltage swing should be around 300 or 400mV, but yours is showing less than 100mV. Even if it's single ended it's still off. Since I can't see your reference level (the ground mark), I can't really tell the common mode. Can you check whether or not other outputs and output formats work well or do they all look the same? I can't really think of any reason as I didn't see this on the bench.

    Regards,
    Hao

  • 0 in reply to Hao Z
    TI__Mastermind 18070 points

    Hi Guido,

    Please make sure that you have the right output termination based on figure 6 or figure 7 of datasheet, depending on whether you use AC coupling or DC coupling for the outputs.

    Regards,
    Hao

  • 0 in reply to Hao Z
    TI__Mastermind 18070 points

    Hi Guido,

    Found something else while I was cleaning up the register stuff. So unlike CDCE6214-Q1, for which using 1.8V output under 3.3V supply may damage the part, the 1p8Vdet register in CDCI6214 is recommended to be set to high all the time. So this register adapts the common mode of LVDS output, however, the swing and common mode trimming are adjusted based on 1p8Vdet = 1. That's why the common mode and swing were off when this register was set to 0.

    Regards,
    Hao