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CDCLVC1102: input slew rate questions for 3.3 V cmos 160 MHz clock input

Howard Bandell
Intellectual 555 points
Part Number: CDCLVC1102

Wondering if you can handle .8-.9 nsec/V min slew rate - for a 160 MHz clock signal coming from ABLJO-160MHz device.

Says output rise and fall time can be 4 nanoseconds worst case.

  • 0
    TI__Mastermind 18070 points

    Hello Howard,

    This ticket has been assigned. My coworker will get back to you soon.

    Regards,

    Hao

  • 0 in reply to Hao Z
    Intellectual 555 points

    Is there a better cmos buffer I should pick? I will be feeding a DAC with it. 160 MHz clock.

  • 0 in reply to Howard Bandell
    TI__Genius 16845 points

    Hi Howard,

    The minimum input slew rate for the CDCLVC1102 is 1 V/ns. It can support 0.8-0.9V/ns input slew rate, but this operating point is outside of the recommended operating conditions, therefore you might get performance that exceeds the electrical specifications. Mainly, slower slew rate can increased jitter and increase the noise floor, please make sure that it meets the requirements for your DAC.

    For a 1:2 3.3V LVCMOS buffer, CDCLVC1102 is the best recommendation. Please let me know if you have additional requirements and we could consider other buffers.

    Kind regards,
    Lane