LMK04828: How to adjust SYSREF delay if you don't have a scope capable of looking directly DCLK?

David Marcos1

Part Number: LMK04828
Other Parts Discussed in Thread: LMK04832

Hi,

We're working on synchronizing two high speed ADC's clocked at 2457,6 MHz by an LMK04828, using direct VCO output.

The ADC's require a couple of SYSREF pulses for synchronization referenced to an internal CLK/2 clock rising edge and we need to meet setup and hold times for proper sysref pulse capture with no ADC clock cycle uncertainty. The SYSREF also goes to an FPGA. We already got the SYSREF pulse mechanism to work as we want and verified that it does indeed work

One of the ADC's uses DCLK/SDCLK from the same group and the other from different LMK04828 groups due to layout constraints. The PCB uses high speed stackup for high speed signalling and the SYSREF/DCLK pairs for each ADC are length matched.

The clock that samples and captures the ADC SYSREFs are 1228,8 GHz with a period of 814ps. The ADC requires 160ps setup and 480ps hold times referred to the rising edge of this clock. The analog delay for sysref works in 150ps steps and according to the datasheet of the LMK04828 the maximum skew between outputs in different groups is 50ps.

If our math is correct, it should always be possible to delay the sysref to a point where constraints are met with significant margin to spare for uncertainty.

However, we need to know our starting point and that's where things get tricky. We have test outputs availble and we've used to test the SYSREF generation with our scope, but our best scope only has 1 GHz bandwidth. Direct observation of the sysref/sysclk pairs at our DCLK frequency of 2457,6 MHz is impossible for us. As we're using direct VCO output, digital delay would be futile so we're left with the analog delay for SYSREF.

Also, due to some constraints, DCLK has to be LVPECL1600 and SYSREF must be LVDS for both ADC's. We can't find a reference in the datasheet on what skew to expect between our SYSREF pulses's rising edges and our DCLK clocks rising edges if all digital delays (local or global) are turned off, to get a baseline for adjusting the analog delay to a point where it guarantees proper SYSREF pulse capture every time.

Any ideas on how this could be achieved or do we need to borrow/rent a better scope for this?

Our L

over 5 years ago

0 Lane Boyd over 5 years ago

TI__Genius 16845 points

Thanks for posting on E2E. I have assigned your post to the responsible engineer. He will respond to you soon.

Kind regards,
Lane

0 Derek Payne over 5 years ago

TI__Mastermind 33490 points

Hello David,

Apologies for the delay. We haven't characterized that value, so I can't say with certainty. We could provide an estimate for a single part, but that wouldn't give you a clear picture across process/voltage/temperature. I think you may be better off calibrating with a test pattern into the ADC, and examining the output with different analog delay settings to find the valid set of values for SYSREF ADLY; then pick a number that sits right in the middle of the window of valid setup/hold time. This kind of skew measurement is difficult to perform adequately even with the proper equipment. Note that the LMK04828 datasheet only provides a maximum skew measurement for one use case, and that case is where the clocks are identical; the rest are typical measurements, which are not assured.

I'm not clear on the math you are using to meet setup/hold constraints with significant margin for uncertainty. As I understand it, the SYSREF signal must not change during either the setup or the hold time, leaving a valid window of 814ps - 480ps - 160ps = 174ps. So with an analog delay step size of 150ps, you can end up with an edge located very close to the edge of the valid window. For example, even if the edges of the DCLK and the SDCLK are typically perfectly aligned, enabling analog delay with a step value of 0 puts the SYSREF edge just 20ps away from the end of the hold time. LMK04828 ADLY has a lot of variation over temperature, ±50ps across full range. If your application is subject to temperature cycling, even within the 0-40°C range, you can find yourself outside of the valid SYSREF window. And that doesn't even take into account the variation in skew between outputs across process, voltage, or temperature.

I recommend looking at the LMK04832 instead. LMK04832 is P2P-compatible with LMK04828, but the ADLY steps are about 21ps, the range is about 480ps, and the temperature variation is about ±5ps across temperature for any step. The smaller step size also gives you at least seven different step values that should fall within the valid SYSREF window.

Regards,

0 David Marcos1 over 5 years ago in reply to Derek Payne

Prodigy 110 points

Hello,

We will definitelly consider the LMK04832 for future revisions of this product, as it has very significant advantages on other areas that would be very convenient for our application and it's a much better choice.

About the SYSREF math, I wrote from memory and surely I was totally wrong. You're right, the math with the values I gave does not add up. I actually mixed up several numbers. The hold time I gave is not the hold time in the canonical sense but the minimum SYSREF pulse duration, and I mistyped it as it's actually 840ps instead of 480ps.

The actual hold time in the sense of how long does the sysref signal need to be static after the rising clock edge is much shorter, the window for SYSREF change that we have is close to 500ps and that gives us enough margin.

0 Liam Keese over 5 years ago in reply to David Marcos1

TI__Genius 12705 points

Hello David,

Thank you for the follow up. Glad to hear you have enough margin for your design.

Regards,

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LMK04828: How to adjust SYSREF delay if you don't have a scope capable of looking directly DCLK?