LMK04808BEVAL: PLL2 0-delay

Hello Jingjun,

The problem here is that CLKout8 is being used as feedback clock.  That clock is 1474.2 MHz.  The reason this was done is because it still allows the frequencies to display properly.

In your case where you want 0-delay to work at a 122.88 MHz, you must feedback the lower frequency to the PLL2 N.

Observe from functional block diagram in section '8.2 Functional Block Diagram' of the LMK04808 datasheet that in 0-delay mode, the FB Mux is fed directly into the PLL2 N2 Divider.  Therefore to enable 0-delay at 122.88 MHz output frequency using your configuration,

1) On Use Control page, update the FEEDBACK_MUX from CLKout8 to CLKout0.  This selects a clock output at 122.88 MHz for feedback to PLL2 N.

2) On the PLL2 page, change the PLL2 N value from 12 to 1.  Because the 122.88 MHz of CLKout0 is now is delivered to PLL2 N divider, by setting PLL2 N = 1 the phase detector will be 122.88 MHz from CLKout0.  Now we satisfy the two equations for PLL2 phase detector frequency.

After doing this, because the EVM GUI does not support 0-delay frequency calculations, the VCO will be calculated incorrectly as 122.88 MHz * 1 (PLL2_N) * 2 (Pre-N Divider).

It should use the equation 122.88 MHz * 1 (PLL2_N) * 24 (CLKout0_DIV).

Please try these two updates with your config.

73,
Timothy

Timothy

Your suggestion is very helpful.  Following your step "PLL2 0-delay" works on LMK04808B Evaluation Board.

I have the following concerns: If the OSCin is 125MHz 30% duty cycle or sinusoidal signal instead of 50% duty cycle clock on the evaluation board.  can  the "PLL2 0-delay" work? Is there a way that I can test this in the evaluation board?

 OSCin input has a multiplier X2.  How does it work? Does this mean the 30% duty cycle or sinusoidal input on OSCin will work?

Thanks

Jingjun

Hello,

If your input duty cycle is 30%, 0-delay can still work.

You should never use doubler with non-50% duty cycle input, there will be bad spurs.

This would work with a sine wave.

To test on EVM, use an oscope to probe the input and output at the same time, then you should see deterministic phase every time you power down/power-up and re-program.

73,
Timothy

Timothy

To avoid the impact of OSCin clock with 30% duty cycle, I have set the PLL2 "R Divider" to 2. In this case Phase detector will work at 61.44MHz. I still want to keep PLL2 0-delay for 122.88MHz at the output, I set Pre-N-Divider to 4 instead of 2. Why cannot I get the "PLL2  Int VCO 0-Delay" work? Is there any trick for this configuration?

Thanks

Jingjun

Hello Jingjun,

In zero-delay the Pre-N-Divider is bypassed.  You need to double the value of the N divider to cause lock since you halved the phase detector frequency.

A detail I didn't mention initially, during VCO calibration which occurs immediately after programming the PLL2_N register, the device does not operate in 0-delay mode.  Rather the VCO will be calibrated to the frequency of PDF * PLL2_P * PLL2_N_CAL, then it switches to zero-delay mode which using the clock output divider, and PLL2_N.  So increasing the PLL2_P value from 2 to 4 addressed the VCO frequency being proper for calibration, or you could change the PLL2_N_CAL value which is in the User Control tab of the GUI.  It is in the Others --> PLL2 sub group.  On the right hand side on my screen.

Please refer to section 9.1.5 PLL Programming of the datasheet.

73,
Timothy