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LMK04832: SCK and SDIO

Part Number: LMK04832

Hi team,

Few questions about timing requirement:

1. What's the "when VCO is in lock" mean in below marked sentence?  It means during the lock time or after VCO is locked?  

2. When SCK and SDIO is toggled, how much will the phase noise be degraded?

3. How to avoid or relieve this PN performance degrade?

Thank you.

  • Thanks for posting on E2E. I have assigned your post to the responsible engineer. He will respond to you soon.

    Kind regards,
    Lane

  • Hello Lilian,

    1. After the VCO is locked.

    2. This depends on many factors, including slew rate of the SCK/SDIO edges, SPI clock speed, location and impedance of bypass capacitors, and PCB layout parasitics. But for example, if SCK rate is 10MHz, you may see a 10MHz spur and harmonics coupling into the outputs while SCK is running.

    3. Here are some suggestions:

    • A low-pass filter on the SPI signals can help remove higher order harmonics from the square wave signals, but make sure the filter does not reduce the slew rate of SPI signals below 30V/µs.
    • Use the datasheet recommended bypass capacitance for supply pins, and keep bypass paths close to the IC.
    • Keep the path of the SPI signals (and ground return loop for SPI signals) away from the PLL signals, especially the VCO supply and bypassing (pins 10, 11, 12), and the input/charge pump pins (pins 32 to 48).
    • Group signals with lower phase noise requirements on clock group 1 (CLKout2, CLKout3) if possible.
    • It can sometimes help to change the SPI clock speed so that the major interfering frequency is outside the bandwidth of interest, though this is not always practical.
    • For shared SPI buses, it may be helpful to gate the SCK/SDIO signals with the CS* signal. A low-cost OR gate with the CS* signal should hold the SCK/SDIO signals at DC high until CS* for the LMK04832 is deasserted.

    Regards,