LMK04610: LMK04610

Hello Thiri,

The most common issue we see with generating SYSREF pulses is that the internal digital clock for PLL2 must be slower than the SYSREF output frequency. For example, if the PLL2 phase detector is set to 200 MHz, and the SYSREF frequency is set to 10 MHz, PLL2_REF_DIGCLK_DIV should be set to 32 so the internal reference clock is reduced to 200/32 = 6.25 MHz, which is less than the SYSREF output frequency of 10 MHz. If it is not possible to set the internal digital clock slower than the SYSREF frequency, the SYSREF pulse cannot be generated with the procedure in 9.3.7.4.2.

If the above condition is satisfied, and the procedure of 9.3.7.4.2 is still not successful, can you please provide the register programming for the LMK04610, either as .tcs file or as raw hex dump?

The per-channel static digital delay should be usable for SYSREF outputs, providing a controllable delay in VCO post-divider clock cycles for SYSREF channels independent of the other system outputs. Alternately, an external control signal (SYSREF_REQ) could be used to control when the SYSREF output becomes enabled.

Regards,

Hi Derek,

Thank you for quick response. I just found out that we are using bypass mode, bypassing both PLLs . That case I think it might not be possible for SYSREF pulsing . Is that correct or is there any other way we can generate single or gapped pulse ?

Also since we are bypassing PLLs, I guess we wont be able to use static digital delay either, but should be able to use SYSREF_REQ in periodic mode. is that correct ?

Thank you,

Thiri