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LMK00105: Interface with 3.3V CMOS crystal oscillator whose output current is up to ±4mA

Part Number: LMK00105

Hi team,

My customer considers to use LMK00105 and provided some questions.

  1. They considers to use 3.3V CMOS single-ended output crystal oscillator (slew rate of about 0.3V / ns) as a clock source.
    In this case, they should connect it to CLKin pin.
    Is this understanding correct?
  2. In “8.1.1 Clock Inputs” of the LMK00105 Datasheet, a 50Ω terminated example is described.
    However, max output current of 3.3V CMOS crystal oscillator only has ±4mA.
    What should they do in this case?

I'm looking forward to hearing back from you.

Best regards,

Shota Mago

  • Hi Shota,

    Please note that for LMK00105, maximum single-ended input swing VI_SE is 2Vpp MAX (datasheet table 6.5). The 50-ohm is recommended to attenuate the swing of the input clock if it is 2.5V or 3.3V LVCMOS to less than 2V.

    Consider using a 1.8V oscillator. Yes, connect it to CLKin like datasheet figure 6.

    Kind regards,
    Lane

  • Hi Lane-san

    Thanks for your reply.

    • If the customer chose 1.8V oscillator, is it possible to connect oscillator to CLKin pin directly w/o any component?
    • Oscillator has no more than ±4mA current capability.
      If the customer connect oscillator like figure 6, is there no problem?

    Best regards,

    Shota Mago

  • Hi Shota,

    If the customer chooses a 1.8V oscillator, they can connect it to CLKin like figure 6 and they do not need the 50-ohm resistor.

    Kind regards,
    Lane

  • Hi Lane-san

    Thanks for your reply.

    Let me ask you additional question.

    Is there minimum requirement for input slew rate?

    i.e. Is there any effect except for degrading jitter performance?

    Best regards,

    Shota Mago

  • Hi Shota,

    It is recommended to use an input with slew rate of 2 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter.

    We do not specify a minimum slew rate, but it is important to understand that will also limit the maximum frequency. For example, assume VDD = 3.3V and slew rate = 1V/ns. In this case, you will have ~6.5ns of rising and falling edge per period, limiting the maximum frequency to 153.8MHz.

    Kind regards,
    Lane