Part Number: LMK04832EVM
hi,
we are testing LMK04832EVM and we are facing some challenges with automatic mode of the input clock switching as described in paragraph 8.3.6.3.
We have used default setting of LMK04832EVM (except clock selection) and we have connected two signal generators to ClkIn0 and ClkIn1 (both set to 122.88 MHz). Board was using CLkIn0, both PLLs were locked and output jitter was in spec.
Then we started to decrease output level on SG connected to ClkIn0 to see when automatic switch to ClkIn1 will appear.
When level was at -14 dBm (i.e. 126 mVpp) PLL1 lost lock (lock detected signal becomes low) same for -15 dBm and when level was decreased further to -16 dBm switch to ClkIn1 was made and PLL1 gets locked.
We will monitor both PLL lock detects anyway in actual design, so we can force ClkIn switch via SPI, but I wonder if there is some setting which can prevent this switching ”hysteresis”.
thanks a lot in advance
KR
Vincenzo
