Other Parts Discussed in Thread: LMK03318, CDCE6214-Q1
Problem:
We have programmed the CDCE's internal clock source to be 1 GHz (default from the reference design and set up by the FPGA). We're only changing the independent output divider for each output.
By design, each output port of the clock generator should be (and must be) independent from each other. So if our SW changes the output divider ratio of Port 0, it should not affect the other 4 outputs.
But the reality is: it does affect the other 4 outputs, and the outcome is quite serious: When Port 1 (U1) is disturbed while we change port 0, the SGMII link between MAC and PHY is broken, causing the DSP to lose connection with the PC, other Ports (U2-U4) are also affected by changes of the output divider ratio of Port 0.
It's the mere action of writing to the CDCE registers that is causing the issue, apparently. If I just try to turn off Port 0, it will also cause disturbance to other ports. Even writing the same data to the same register causes disturbance to other ports. So it's not output frequency change, it's just the mere access to port register, that is causing instability to outputs of other ports.
I would like to know what factor may cause this issue, or if it's possible that the CDCE62005 chipset currently used is a defective one or damaged one?
Thank you.
Stanley