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Default Outputs of Unprogrammed CDCE62005

Vinay57187
Prodigy 50 points

Hi,

We have 80MHz (LVCMOS compliant) oscillator output fed to the PRI IN & 38.4MHz AT Cut Crystal to AUX IN of the PLL. At the time of powering the board (those that have come from FAB house), the PLL would be unprogrammed. In page 25 of the datasheet, they specify the default values of EEPROM that shall loaded in the RAM. However, it is mentioned that "Reference is set at 25MHz".

  1. We wanted to know, how the said 25MHz would be available for the PLL?
  2. Should we provide external 25MHz oscillator output to the SEC IN pin?
  3. How can the user control the EECLKSEL bit?
  4. Even with 80MHz (to PRI IN) and 38.4MHz (to AUX IN) clocks fed to the PLL, would we still continue to receive -

  1.  
    1. Output 0 & 1 are set to output 156.25MHz with LVPECL signaling
    2. Output 2 is set to output 125MHz/ LVPECL
    3. Output 3 is set to output 125MHz/ LVDS
    4. Output 4 is set to output 125MHz/ LVCMOS

Request your kind support.

Thanks and Regards,

Vinay

  • 0
    TI__Genius 13335 points

    Hello,

    1.The default settings in the datasheet assume there is a 25 MHz input at PRI IN or a 25 MHz crystal at AUX IN. The smart mux is setup by default such that it will try to detect a signal at PRI IN first and if none is found it checks SEC IN, then AUX IN. The PLL will lock if a 25 MHz reference is provided using the default configuration. However, If the input frequency is different than 25 MHz, the EEPROM will load the register values, but the PLL will not be locked.

    2.You do not need to provide 25 MHz to SEC IN for your application.

    3.The EECLKSEL bit can be toggled through the GUI by clicking on the "Smart MUX" or through Register 5, bit 5.

    4.No, the output frequency is dependant on the reference frequency and the PLL settings. Using the default settings with 80 MHz (to PRI IN) and 38.4 MHz (to AUX IN), the PLL will not lock. You must first update the PLL settings before the device will lock.