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CDCM7005

Farouk Imami
Prodigy 20 points
Other Parts Discussed in Thread: CDCM7005

Hello,

 

I need some confirmation on a possible application for the CDCM7005 clock synchronizer:

I need a 36kHz signal synchronized with a 25Hz signal. Could you tell me if it is possible? and if it is, if the following parameters are ok:

 

PRI_REF => linked to the 25Hz signal

VCXO_IN => linked to a 8MHz clock

reference divider M => 0

VC(X)O feedback divider N => "010110100000" (divided by 1440)

 

What I would like to know (if what I said earlier is possible..):

how do I tell the component that I want the VCXO output frequency to be 36kHz?

What is the purpose of the LVPECL signal combination? Can I only use (for my application) the Y0A output ?

 

thanks for your time,

 

Regards,

Farouk Imami

  • 0
    TI__Mastermind 20900 points

    Farouk Imami,

    if you want to have 36kHz at the output, you need to have a VCXO of smaller than 576kHz. The CDCM7005 can just divide the VCXO frequency by 16 and down to 1.

    So the smallest output clock you will achieve with an 8MHz VCXO clock is 500kHz.

     

    Furthermore, you need to configure the dividers in this way, that you will have the same frequency in front of the PFD. Therefore, you need to divide the VCXO clock by 320000 (8Mhz/32000 = 25Hz), but we don't have such a big divider.

     

    Best regards,

    Julian

  • 0 in reply to Julian Hagedorn
    Prodigy 20 points

    Julian said:

    if you want to have 36kHz at the output, you need to have a VCXO of smaller than 576kHz. The CDCM7005 can just divide the VCXO frequency by 16 and down to 1.

    I don't understand.. In the page 22 of the CDCM7005 datasheet (that I found here: http://pdf1.alldatasheet.com/datasheet-pdf/view/107113/TI/CDCM7005.html), I can see that the VCXO feedback divider value can go up to 4096 (12 bits), and the reference divider value up to 1024 (10 bits).

     

    In any case, If I manage to divide (with an other component) the 8MHz clock to have a 36kHz signal in the VCXO_IN, will it be ok?

     

    Regards,

     

    Farouk Imami

     

    EDIT:

    Sorry, after reading again and again the datasheet, I now understand that the output signal can only be the VCXO_IN signal divided by 16 max.

    But then again, if I manage to have a 36kHz signal in the VCXO_IN, and to configure the N_divider to be at 1440, will it be ok? (I mean by that: will I have a 36kHz signal synchronized with a 25Hz reference signal?)

     

    Thanks again for your time.

  • 0 in reply to Farouk Imami
    TI__Mastermind 20900 points

    Hello Farouk,

    with a 36kHz signal at VCXO_IN and a 25Hz reference signal the CDCM7005 would work correctly. You have to ensure, that both frequencies, which will be fed into the PFD, have the same frequency. The PFD compares both Phase and Frequency.

    Regards,

    Julian

     

    btw:

    I think it will be a difficult task to divide a 8 MHz signal to a 36kHz signal, because you will have to divide the 8MHz by 222.222. Maybe it is easier to divide by 320 and set the N_divider to 1000. This will have the same effect, with the exception of, that you have a 25kHz signal at VCXO_IN instead of 36kHz.