SN65LVEP11: reducing common mode output voltage

Hi,

We are planning to use SN65LVEP11 for converting LVDS signal from FPGA to LVPECL for connecting to ADC12DJ3200 time-stamp pins.

Time -stamp pins of ADC12DJ3200 can be used as JESD204b sync also for ADC and since this is a low duty cycle signal it is recommended to DC couple the LVPECL signal to time-stamp pins of ADC12J3200.

Now LVPECL standard specify 2v as common mode voltage.

But ADC12DJ3200 time-stamp pins supports only 0.5v max common mode voltage.

So some additional resistor divider or other circuitry is required at output of SN65LVEP11 to reduce the common mode from 2v to 0.5v but at the same time swing should be more than 0.4vpp which is required by ADC12DJ3200 time-stamp pins.

I have tried the below circuit with SN65LVEP11 ,in which LMK04828 LCPECL output common mode is reduced using resistor divided to connect to sysref pins of DAC38J84 which also supports common mode of 0.5v.

But in my case common mode is coming around 0.9v.

So can you guys please suggest a circuit to DC couple the SN65LVEP11 LVPECL output to timestamp pins of ADC12DJ3200 with common mode of 0.5v with sufficient swing.

An early response will be highly appreciated.

Thanks,

Lalit