Part Number: CDCI6214
Hi,
I'm working on a new design with CDCI6214 as a proposed clock generator. I've gone through the datasheet several times, and read most of the TI forum items on this part, but some aspects are still unclear to me. I hope that someone can help me with that.
Baseline:
- VDDREF = VDDVCO = VDDO12 = VDDO34 = 1.8V.
- One fixed REF CLK source, single ended 100MHz 1.8V LVCMOS
- EEPROMSEL = REFSEL = HIGH
- Configuration via I2C interface after powerup. I don't want to program the EEPROM
- Only 2 outputs needed, both 250MHz LVDS. Settings will not change after powerup configuration
REF CLK input
- What input can I use best for the single ended REF CLK? Datasheet suggests that I can use either REFP (pin 5) or XOUT (pin 1) in LVCMOS mode for this. Is there a preference for one or the other? Lowest power consumption is relevant for my design.
- On my board the distance between my REF CLK source and CDCI is only a few mm. Do I need termination as suggested by datasheet figure 3, or can I just use DC coupling (through a series resistor) from my CLK source to the REFP or FB_P input pin?
- What should I do in hardware with the REFN or FB_N pin? Keep it open? Connect to GND? Are there relevant register settings that I need to apply?
- Assuming that I use the REFP (pin 5) as the reference input, what should I do with the XOUT/XIN pins? Keep open? Connect to GND?
Configuration control
- I'd like to override the EEPROM settings and do complete configuration at each powerup by writing all registers through the I2C interface. Reason for this is that we build small production series and don’t want to invest in EEPROM programming facilities or scripts in the factory. Is that feasible? Are there any special actions required for this, e.g. hard or soft reset after setting the registers, PLL calibration?
Output signals
- At this moment I only need 2 outputs. Both should be 250MHz LVDS outputs, but the 2nd signal must be inverted, i.e. have a defined 180degree phase w.r.t. the 1st signal. What would be the best approach to reach this? I’m thinking of running VCXO at 2500MHz, use pre-scaler A with divider=5 for both channels, followed by sync_delay=0 for the first channel and sync_delay=1 for the second channel, and then both channels IOD=2.
- Will that work reliably?
- How accurate will the phase relation be between the 2 signals?
- Is there another approach possible to get the same result?
Best regards,
Paul
