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LMK04828: Clock tree synchronization of multiple RFSoC boards

Lalit Chaudhari
Prodigy 40 points
Part Number: LMK04828
Other Parts Discussed in Thread: LMX2594, TIDA-01023, TIDA-01024

Hi,

I did go through below link,

https://e2e.ti.com/support/clock-and-timing/f/48/t/819699?LMK04828-Multiple-RFSoc-Clock-Tree-Synchronization

But it didn't clarify few things for our use case. We have a requirement to synchronize eight RFSoC boards in a chassis and also need an option to synchronize multiple (at least 2) chassis for horizontal scaling. Please see attached clocking diagram and let us know if it will work for our use case.

ADC and DAC sampling frequency: 4096 MSPS (fixed)

Few questions:

1. Master LMK04828 operating modes. In single chassis mode, it will operate in single loop mode with vcxo. While in multi-chassis case, one chassis in single loop mode will send out REFCLK_OUT and SYNC_OUT to other chassis. Will this work?

2. On FPGA  card, SYNC signal for LMX device is continuous or single pulse or not needed?

3. On Backplane, Master DCLKout0 is differential or single ended? Should it be DC coupled? Is it same for Slave12 DCLKOut0?

4. All Slave LMK devices operate in Distribution mode? so does not require VCXO?

  • 0
    TI__Mastermind 28001 points

    Lalit,

    I am not sure of the answer to this, but I assigning this to someone who hopefully knows more.

    This looks like you are using the LMK04828 in distribution mode as a JESD204B buffer, which is a legitimate use case we have seen before.

    I'm not sure of the AC/DC coupling.

    Regards,

    Dean

  • 0 in reply to Dean Banerjee
    Prodigy 20 points

    Hi Dean,

    On the datasheet of LMK0482x, the CLKin should be "AC-coupled".

    10.2.2.1 Driving CLKin PINS with a Differential Source
    Both CLKin ports can be driven by differential signals. It is recommended that the input mode be set to bipolar
    (CLKinX_BUF_TYPE = 0) when using differential reference clocks. The LMK0482x family internally biases the
    input pins so the differential interface should be AC coupled. The recommended circuits for driving the CLKin
    pins with either LVDS or LVPECL are shown in Figure 20 and Figure 21.

    But the TIDUDS0 doc recommended,

    The DCLKout0 and DCLKout2 output signals of the master are fed to the slave LMK04828s at CLKin1.
    The master then sends the DC-coupled sync pulses through SDCLKout1 and SDCLKout3 to the slaves for
    synchronization. Later, the LMK devices of the slaves generate the synchronized reference, SysRefReq,
    and SYNC signals to LMX2594 of the clocking boards and FPGA clocks to capture cards.

    In the master LMK04828 EVM board, the SDCLKout1 and SDCLKout3 outputs must be modified for DC-
    coupled sync output signals. Remove the circled resistors R104, R112, R126, and R134 and replace
    capacitors C48, C52, C54, and C58 with 0603 0-Ω resistors

    All AC-coupled capacitors are replaced with 0-ohm resistors. Please confirm it.

    Thanks,

    Joon/NPS.

  • 0
    TI__Genius 12560 points

    Hi Lalit, Joon,

    Please see my response to your queries below:

    Lalit Chaudhari said:

    1. Master LMK04828 operating modes. In single chassis mode, it will operate in single loop mode with vcxo. While in multi-chassis case, one chassis in single loop mode will send out REFCLK_OUT and SYNC_OUT to other chassis. Will this work?

    For multi-chassis case, you can follow the TIDA-01024 reference design, which demonstrate the daisy chain configuration for high channel count clock generation. Section 2.3.1 in tiduds1 doc shows the board to board clock sync in daisy chain configuration.

    Lalit Chaudhari said:

    2. On FPGA  card, SYNC signal for LMX device is continuous or single pulse or not needed?

    All the SYNC signals to each LMX and slave LMK should be single pulse or number of pulses but not be continuous. 

    Lalit Chaudhari said:

    3. On Backplane, Master DCLKout0 is differential or single ended? Should it be DC coupled? Is it same for Slave12 DCLKOut0?

    On the datasheet of LMK0482x, the CLKin should be "AC-coupled".

    If slave LMKs are using Balun at CLKin1 input, then Master LMK DCLKout0 / 2 would be single ended else provide the differential outputs. DCLKouts are input reference signals at CLKin1 of slave LMKs hence it should be AC coupled, whereas SDCLKouts are using as SYNC through CLKin0 of slave LMKs, which should be DC-coupled for high performance synchronization.

    Lalit Chaudhari said:

    4. All Slave LMK devices operate in Distribution mode? so does not require VCXO?

    To get an best performance from LMX2594, OSCin signal of the LMX should be as clean a possible. In present architecture, OSCin of the LMX2594 comes from LMK04828 and all OSCin signals should be synchronized also. Hence, individual VCXO are not required for each slave LMK devices. But slave LMKs can be operate in PLL mode or distribution mode as per performance needed.

    To provide the option of slave LMKs in PLL mode, one suggestion would be provide the connection provision to the OSCin as well of slave LMK from DCLKout of Master and/or adjacent LMKs.

    Hope the above responses clarify your queries.

    Thanks!

    Best Regards,

    Ajeet Pal 

  • 0 in reply to Ajeet Pal
    Prodigy 40 points

    Thank you Ajeet for the clarifications.

    Is it possible to get .tcs files for TIDA-01023 and TIDA-01024?

  • 0 in reply to Lalit Chaudhari
    Prodigy 20 points

    The datasheet stated that The LMK0482x family internally biases the input pins so the differential interface should be AC coupled.

    And both Master/Slave devices are LMK04828, there is NO WAY to have the DC-Coupled differential signal unless it's a single-end.

    Thanks, Joon

  • 0 in reply to Lalit Chaudhari
    TI__Genius 12560 points

    Hi Lalit,

    Some of the .tcs files for TIDA-01023 reference design are already available on SW folder of the same design.

    Please share your email id on ajeet.p@ti.com; I'll send the remaining files on email.

    Hi Joon,

    CLKin input signal should be AC coupled, when it uses as reference signal.

    As mentioned in previous reply, CLKin0 port of the slave LMKs are using for SYNC signal input, which should be DC-coupled for high performance synchronization.

    Thanks!

    Best Regards,
    Ajeet Pal