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LMK04208: LMK04208 configuration

Shinu.V.Mathew
Genius 11930 points
Part Number: LMK04208


Hi Team,

One of my customer is using LMK04208 for ZCU111 Xilinx RFSoC. The output Clock frequencies required is as below.

  1. OUT0 -> 7.68 MHz
  2. OUT1 -> 7.68 MHz
  3. OUT2 -> 245.76 MHz
  4. OUT3 -> 491.52 MHz
  5. OUT4 -> 491.52 MHz

 The inputs:

CLKIN0 -> 122.88 MHz

CLKIN1 -> terminated in connector 

Customer requirement is: Feed 10MHz to CLKIN1. Do not use CLKIN0.

Customer have arrived on the values for the configuration they require. Can you please review/validate the attached configuration?

Regards, Shinu Mathew. 

  • 0
    TI__Genius 11930 points

    Configuration file attached.

    PLL_Config.tcs

    Thanks, Shinu Mathew. 

  • 0 in reply to Shinu.V.Mathew
    TI__Genius 11930 points

    Hello Team,

    Can you please help on this.

    Regards, Shinu Mathew.

  • 0 in reply to Shinu.V.Mathew
    TI__Genius 11930 points

    Hi Team,

    Can you please help on this request.

    Regards, Shinu Mathew

  • 0 in reply to Shinu.V.Mathew
    TI__Genius 9920 points

    The configuration has some problem for 0-delay feedback. Please clarify what's the synchronization requirement for 10 MHz input and other outputs.

    Normally, we will adopt the lowest output frequency as the feedback clock, then other higher frequency clocks (= n * feedback clock, n is an integer) can be aligned on the same rising edges.

  • 0 in reply to Shawn Han
    TI__Genius 11930 points

    Hi Shawn,

    "Please clarify what's the synchronization requirement for 10 MHz input and other outputs”.

    Not Sure what inputs you need for above point. Are you asking about the stratum level? Customer indeed want all the outputs to be synchronized to the inputs. Inputs are 12.8MHz and 10MHz. Output requirements are shared already. 

    Customer tried the attached configuration, 0-delay and dividers are fine. 

    However, they have trouble performing “switching between two clock inputs”.

    When the other CLK (CLKIN0) is enabled, the PLL1 does not lock. PLL1 locks when only one of the clocks are enabled. Please note the R-divider is kept same for both inputs as recommended.

    Please help to close this as early as possible.

    Regards, Shinu. 

  • 0 in reply to Shinu.V.Mathew
    TI__Genius 9920 points

    1, Input the correct clocks for CLKin0 and CLKin1, find the Greatest Common Divisor (GCD) frequency for CLKin0 and CLKin1, which could be used for PLL1 phase detect frequency. Set CLKin Dividers and R divider for CLKin0 and CLKin1, if different CLKin Dividers can't get the same output frequency, then we need change R divider when switching to another CLKin.


    2, Feedback clock: Select the lowest output frequency in all outputs need to be synchronized. Here 7.68 MHz may be your preferred.


    3, Set N divider for PLL1 to achieve the same frequency as R divider path.

  • 0 in reply to Shawn Han
    TI__Genius 11930 points

    Hi Shawn,

    Thanks for the feedback.

    Please find the attach file shared by customer can you please check and comment.

    10M_CLKIN1_CLKIN0-DIS-NO-delay-Auto-CLKIN1-PLL1.tcs

    Fullscreen 10M_CLKIN1_CLKIN0-DIS-NO-delay-Auto-CLKIN1-PLL1.txt Download 
    R0 (INIT)	0x00160040
R0	0x00143000
R1	0x00143001
R2	0x00140182
R3	0x001400C3
R4	0x001400C4
R5	0x001400C5
R6	0x01400006
R7	0x04400007
R8	0x04010008
R9	0x55555549
R10	0x910249AA
R11	0x1401100B
R12	0x1B0C006C
R13	0x2302884D
R14	0x0230000E
R15	0x8000800F
R16	0xC1550410
R24	0x00000058
R25	0x02C9C419
R26	0xAFA8001A
R27	0x10001F5B
R28	0x0026001C
R29	0x0180019D
R30	0x0200019E
R31	0x003F001F

    Regards, Shinu.

  • 0 in reply to Shawn Han
    TI__Genius 11930 points

    Hi Shawn,

    Thanks for the feedback.

    Please find the attach file shared by customer can you please check and comment.

    3704.10M_CLKIN1_CLKIN0-DIS-NO-delay-Auto-CLKIN1-PLL1.tcs

    Fullscreen 4527.10M_CLKIN1_CLKIN0-DIS-NO-delay-Auto-CLKIN1-PLL1.txt Download 
    R0 (INIT)	0x00160040
R0	0x00143000
R1	0x00143001
R2	0x00140182
R3	0x001400C3
R4	0x001400C4
R5	0x001400C5
R6	0x01400006
R7	0x04400007
R8	0x04010008
R9	0x55555549
R10	0x910249AA
R11	0x1401100B
R12	0x1B0C006C
R13	0x2302884D
R14	0x0230000E
R15	0x8000800F
R16	0xC1550410
R24	0x00000058
R25	0x02C9C419
R26	0xAFA8001A
R27	0x10001F5B
R28	0x0026001C
R29	0x0180019D
R30	0x0200019E
R31	0x003F001F

    Regards, Shinu.

  • 0 in reply to Shinu.V.Mathew
    TI__Genius 9920 points

    It can work, but why do not use CLKin0 or CLKin1 7.68 MHz as feedback clock ?

  • 0 in reply to Shawn Han
    TI__Genius 11930 points

    Hi Shawn,

    You suggested CLKIN0 or IN1 to br 7.68MHz? If yes, it is not possible. It has to be 12.8M (IN0) and 10M (IN1).

    Or want CLKOUT0, CLKOUT1 as feedback clock?

    Can you please clarify.

    Regards, Shinu Mathew. 

  • 0 in reply to Shinu.V.Mathew
    TI__Genius 9920 points

    10M_CLKIN1_12M8_CLKIN0-NO-delay-PLL1-40kHz_PDF1-CLKout0_FB-1p6mA_CP1-PLL1WND_40ns.tcs

    Here is an example.

    1, Calculate GCD for 10 MHz, 12.8 MHz and 7.68 MHz --- > 40 kHz

    2, Set PDF1 = 40 kHz

    3, Select Feedback_MUX from CLKout0 7.68 MHz

    4, Increase CP1 to 1.6 mA to against VCXO leakage current under low frequency PDF condition

    5, Set PLL1_WND_SIZE to 40 ns in "User Controls" sheet to against VCXO leakage current

    If there is no necessary to use 0-delay, then we can use 200 kHz PDF1 for 10 MHz and 12.8 MHz references, which can defense VCXO leakage current better than lower 80kHz or 40 kHz.

    For the topic about VCXO current leakage, refer to my notes, attached.

    4370.VCXO Leakage Current and PLL Lock v1.0.pdf