Other Parts Discussed in Thread: LMK03806
Dear Who may concern,
Recently, we are purchasing the LMK03806 Chip for clock generation application.
We have a LMK03806 Eval Board (2011-08-29) in our hand for pre-measurement.
When we drawing the PCB layout, we have the doubts about the PCB trace implemented in the Evaluation Board. All the CLK output traces have 3 stage widthes' varations as shown in the figure. We use the ruler measured the trace width from the chip CLK output to the PCB edge SMA port. The innerest trace width is around 8~12mil, the middle trace width is around 20mil, the outtest trace width is 40mil. In order to reduce the reflection of signals, the CLK output trace impedance should be keep at the constant value of 50Ohm right?
Is there any CAD file of this evaluation board, so that we can do some signal integrity simulation based on the PCB trace geometry?
Thanks very much for the concern!