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CDCE913: CDCE913 support in Linux version 4.14.0

Part Number: CDCE913
Other Parts Discussed in Thread: CDCE925, CDCEL913, CDCEL925

Hi all,

We are using Zynq-7000 in our custom board and Linux version 4.14.0.

We are using CDCE913 clock synthesizer in our custom board and have to configure for 100Mhz.

Linux version 4.14.0 has driver for cdce925 and it is mentioned that this driver support CDCE913 also.

I have added the entry for CDCE913 in my dts file as below:

cdce925@65 {
#clock-cells = <1>;
clocks = <&xtal>;
compatible = "ti,cdce913";
reg = <0x65>;
ti,input-clock-type = "xtal";
clock-names = "ref";
clock-output-names = "pll", "pll-switched";
PLL1 {
spread-spectrum = <4>;
clock-frequency = <100000000>, <100000000>, <100000000>;
spread-spectrum-center;
};

xtal: xtal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "xtal";
};
};

I have added the prints in probe to find out that driver is getting called at the booting , and I  can see that probe function is getting called.

But when I probe the output clock I am getting 25Mhz which is the default clock frequency.

I doubt that CDCE913 is not getting configured properly. 

Whether I am missing something in the dts entry ?

Any other configuration is required for CDCE925 driver to work with CDCE913 chip?

Please suggest.

Regards,

Mahima Shanbag

  • Hi Mahima,

    Not sure I understand the question. CDCE913 uses standard I2C interface and doesn't require any driver. What driver are you referring to?

    Regards,

    Hao

  • Hi Hao,

    I think you didnt understand the question.

     CDCE913 chip is connected to Zynq-7000 PS through I2C interface.

    Before I was using Linux version 4.0.0 in which clk-cdce913.c driver was there, I am able to configure the  CDCE913 chip successfully and able to get 100Mhz output.

    I have attached the clk-cdce913.c for your reference.

    clk-cdce913.c
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    #include <linux/clk-provider.h>
    #include <linux/delay.h>
    #include <linux/gcd.h>
    #include <linux/i2c.h>
    #include <linux/lcm.h>
    #include <linux/module.h>
    #include <linux/regmap.h>
    #include <linux/slab.h>
    #define CDCE913_NUM_OUTPUTS 3
    /* CDCE913 registers */
    #define CDCE913_GENERIC_CFG_0 0x80
    #define CDCE913_GENERIC_CFG_1 0x81
    #define CDCE913_GENERIC_CFG_2 0x82
    #define CDCE913_GENERIC_CFG_3 0x83
    #define CDCE913_GENERIC_CFG_4 0x84
    #define CDCE913_GENERIC_CFG_5 0x85
    #define CDCE913_GENERIC_CFG_6 0x86
    #define CDCE913_PLL_CFG_0 0x90
    #define CDCE913_PLL_CFG_1 0x91
    #define CDCE913_PLL_CFG_2 0x92
    #define CDCE913_PLL_CFG_3 0x93
    #define CDCE913_PLL_CFG_4 0x94
    #define CDCE913_PLL_CFG_5 0x95
    #define CDCE913_PLL_CFG_6 0x96
    #define CDCE913_PLL_CFG_7 0x97
    #define CDCE913_PLL_CFG_8 0x98
    #define CDCE913_PLL_CFG_9 0x99
    #define CDCE913_PLL_CFG_10 0x9a
    #define CDCE913_PLL_CFG_11 0x9b
    #define CDCE913_PLL_CFG_12 0x9c
    #define CDCE913_PLL_CFG_13 0x9d
    #define CDCE913_PLL_CFG_14 0x9e
    #define CDCE913_PLL_CFG_15 0x9f
    /* bitfields */
    #define GENERIC_CFG0_DEVID_SHIFT 7
    #define GENERIC_CFG0_DEVID_MASK (1 << GENERIC_CFG0_DEVID_SHIFT)
    #define GENERIC_CFG0_REVID_SHIFT 4
    #define GENERIC_CFG0_REVID_MASK (7 << GENERIC_CFG0_REVID_SHIFT)
    #define GENERIC_CFG0_VENDORID_SHIFT 0
    #define GENERIC_CFG0_VENDORID_MASK (0xf << GENERIC_CFG0_VENDORID_SHIFT)
    #define PLLCFG_N_UPPER_SHIFT 4
    #define PLLCFG_N_LOWER_SHIFT 4
    #define PLLCFG_N_LOWER_MASK (0xf << PLLCFG_N_LOWER_SHIFT)
    #define PLLCFG_N_MAX 4095
    #define PLLCFG_N_MIN 1
    #define PLLCFG_M_MAX 511
    #define PLLCFG_M_MIN 1
    #define PLLCFG_R_UPPER_MASK 0xf
    #define PLLCFG_R_LOWER_SHIFT 3
    #define PLLCFG_R_LOWER_MASK (0x1f << PLLCFG_R_LOWER_SHIFT)
    #define PLLCFG_Q_UPPER_MASK 7
    #define PLLCFG_Q_LOWER_SHIFT 5
    #define PLLCFG_Q_LOWER_MASK (7 << PLLCFG_Q_LOWER_SHIFT)
    #define PLLCFG_P_SHIFT 2
    #define PLLCFG_P_MASK (7 << PLLCFG_P_SHIFT)
    #define PDIV1_UPPER_MASK 3
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Now I have upgraded the Linux version to  4.14.0 and it has clk-cdce925.c driver.

    Here I am attaching clk-cdce925.c driver.

    clk-cdce925.c
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    /*
    * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer
    *
    * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1,
    * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
    * basis. Clients can directly request any frequency that the chip can
    * deliver using the standard clk framework. In addition, the device can
    * be configured and activated via the devicetree.
    *
    * Copyright (C) 2014, Topic Embedded Products
    * Licenced under GPL
    */
    #include <linux/clk.h>
    #include <linux/clk-provider.h>
    #include <linux/delay.h>
    #include <linux/module.h>
    #include <linux/i2c.h>
    #include <linux/regmap.h>
    #include <linux/slab.h>
    #include <linux/gcd.h>
    /* Each chip has different number of PLLs and outputs, for example:
    * The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs.
    * Model this as 2 PLL clocks which are parents to the outputs.
    */
    enum {
    CDCE913,
    CDCE925,
    CDCE937,
    CDCE949,
    };
    struct clk_cdce925_chip_info {
    int num_plls;
    int num_outputs;
    };
    static const struct clk_cdce925_chip_info clk_cdce925_chip_info_tbl[] = {
    [CDCE913] = { .num_plls = 1, .num_outputs = 3 },
    [CDCE925] = { .num_plls = 2, .num_outputs = 5 },
    [CDCE937] = { .num_plls = 3, .num_outputs = 7 },
    [CDCE949] = { .num_plls = 4, .num_outputs = 9 },
    };
    #define MAX_NUMBER_OF_PLLS 4
    #define MAX_NUMBER_OF_OUTPUTS 9
    #define CDCE925_REG_GLOBAL1 0x81
    #define CDCE925_REG_Y1SPIPDIVH 0x82
    #define CDCE925_REG_PDIVL 0x83
    #define CDCE925_REG_XCSEL 0x85
    /* PLL parameters start at 0x10, steps of 0x10 */
    #define CDCE925_OFFSET_PLL 0x90
    /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */
    #define CDCE925_PLL_MUX_OUTPUTS 0x94
    #define CDCE925_PLL_MULDIV 0x98
    #define CDCE925_PLL_FREQUENCY_MIN 80000000ul
    #define CDCE925_PLL_FREQUENCY_MAX 230000000ul
    struct clk_cdce925_chip;
    struct clk_cdce925_output {
    struct clk_hw hw;
    struct clk_cdce925_chip *chip;
    u8 index;
    u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    It is mentioned that clk-cdce925.c is compatible with CDCE913 chip. But After booting when I probe the clock I am getting 25Mhz which is the default value.

    I am not sure whether  clk-cdce925.c is configuring the CDCE913 chip or not.

    Below is my device tree entry:

    cdce925@65 {
    #clock-cells = <1>;
    clocks = <&xtal>;
    compatible = "ti,cdce913";
    reg = <0x65>;
    ti,input-clock-type = "xtal";
    clock-names = "ref"; 
    clock-output-names = "pll", "pll-switched";
    PLL1 {
    spread-spectrum = <4>;
    clock-frequency = <100000000>, <100000000>, <100000000>;
    spread-spectrum-center;
    };

    xtal: xtal {
    #clock-cells = <0>;
    compatible = "fixed-clock";
    clock-frequency = <25000000>;
    clock-output-names = "xtal";
    };
    };

    Now my question is

    Why CDCE913 chip is not getting configured with clk-cdce925.c? Anything I am missing in my device tree entry?

    Please suggest.

    Thanks and Regards,

    Mahima Shanbag 

  • These codes are not developed by TI. Maybe cdce925.c original design target is to match all listed devices, but finally only implement cdce925.

    They are different devices

    – CDCE913/CDCEL913: 1-PLL, 3 Outputs
    – CDCE925/CDCEL925: 2-PLL, 5 Outputs