CDCM6208: PLL lock issue

Janardan M

Part Number: CDCM6208

HI,

I had posted a query on CDCM6208 PLL lock issue. Below is the thread we have discussed.

http://e2e.ti.com/support/clock-and-timing/f/48/p/828716/3122665#3122665

The issue still persist. In our design there are 3 CDCM6208 ICs, out of 3 ICs 2 ICs are working fine. 3rd IC if I give 25MHz as input PLL is not locking but if I give 19.2MHz input PLL is locking. I am still unable to understand this behavior of IC. Please go through the attached link where there is details of the issue.

Thanks,

Janardan

over 5 years ago

0 Hao Z over 5 years ago

TI__Mastermind 18070 points

Hi Janardan,

Does the problem go away if you replace the 3rd IC with another one?

Regards,
Hao

0 Janardan M over 5 years ago in reply to Hao Z

Expert 1115 points

Hi Hao,

We replaced the IC and checked but issue still persist.

Thanks,

Janardan

0 Hao Z over 5 years ago in reply to Janardan M

TI__Mastermind 18070 points

Hi Janardan,

Correct me if I'm wrong. Based on my understanding, there are three CDCM6208 sockets on the board. Out of the three sockets, two of them are consistently working fine but the third one is consistently not working. So it seems to me that the chip itself is fine but something else is wrong with board / software design related to socket 3?

Regards,
Hao

0 Janardan M over 5 years ago in reply to Hao Z

Expert 1115 points

Hi,

Understanding is partially correct, 3rd CDCM is working with input of 19.2MHz but not with input of 25MHz.

Thanks,

Janardan

0 Shawn Han over 5 years ago in reply to Janardan M

TI__Genius 9920 points

Hi,

All 3 CDCM6208 designed with the same schematic, same input from 25 MHz, same output frequencies, with SPI control mode, right ?

If yes, I'll consider the crosstalk between CDCM6208, how about these 3 units positions?

If no, I still guess there are some registers not be optimized in the 3rd units.

Regards,

Shawn

0 Hao Z over 5 years ago in reply to Shawn Han

TI__Mastermind 18070 points

Hello Janardan,

It seems to me that the register settings for 25MHz input may be incorrect. Can you send over your register configurations for 25MHz input? If you can provide information of input type (PRIREF or SECREF, whether or not crystal is used) as well as output frequencies and formats needed then I can create a configuration for you and verify it on the bench.

Regards,
Hao

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CDCM6208: PLL lock issue