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LMX2571: LMX2571 MULT divider

Part Number: LMX2571

Hi Team,

 

I have a question about LMX2571 MULT divider.

 

When MULT_F2 value and Pre-divider value is the same(MULT_F2= Pre-divider=4) and ambient temperature is high,LMX2571 internal VCO doesn’t lock.

 

This is violate following comment but could you let me know the reason why MULT value must be greater than pre-divider value technical point of view?

(MULT value must be greater than pre-divider value)

 

Regards,

Kai

  • Refer to

    8.1.9 MULT Multiplier
    The main purpose of the multiplier, MULT, in the R–divider is to push the in-band fractional spurs far away from
    the carrier such that the spurs could be filtered out by the loop filter.

    Otherwise, we lost the main purpose.

  • Hi Han,

    I have one more question.
    As I described above, When MULT_F2 value and Pre-divider value is the same(MULT_F2= Pre-divider=4) and ambient temperature is high,LMX2571 internal VCO doesn’t lock.

    Regarding this, When we do following procedure, VCO repeats lock ⇔ unlock alternately.
    1. send register setting for certain frequency with MULT_F2=Pre-divier=4
    2. VCO is locked
    3. heat LMX2571 to 50~60C
    4. change Ninteger/NUM/DEN register setting
    5. re_calibrate
    6. VCO is unlocked

    after 6, when we repeat 4 to 5, VCO repeats lock / unlock alternately.

    could you let me know the reason why LMX2571 repeats this lock/ unlock?

    Regards,
    Kai

  • Kai,

    TI cannot endorse violating this restriction.

    I characterized the MULT of the LMX2571 over temperature and found that the requirement that PLL_R_PRE<MULT was necessary for reliable locking.

    I tried this on normal, slow, and fast corner lots and saw this issue, especially at higher temperatures.  See the attached plot

    This characterization was a while ago, but design told me that this had something to do with the timing.  You can see below on the first column is PRE_R and the other columns are MULT.  The value is the number of failures.

    PRE_R (below)

    3

    4

    5

    6

    7

    2

    0

    0

    0

    3

    4

    0

    0

    0

    0

    4

    7

    1

    0

    0

    0

    5

    0

    1

    1

    0

    0

    6

    2

    2

    1

    0

    7

    2

    3

    0

    8

    0

    4

    1

    9

    2

    2

    10

    0

    0

     

    Regards,
    Dean