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CDCE813-Q1: Question for Application and Implementation

Kazuki Kitajima
Intellectual 1480 points
Part Number: CDCE813-Q1

Hello team,

I'd like to confirm this device. In the DS p21 Typical Application, there's a resistor divider to shift voltage level.

Is it allowed to add a divider like a pic below in the case of 65.5MHz PCLK?

The customer's clock is 3.3V which exceeds the recommended spec(1.9V) in DS.

Thank you,

Kazuki Kitajima

  • 0
    TI__Mastermind 18070 points

    Hi Kazuki,

    Yes it is OK to add a resistor divider like this. There is a trade off when choosing resistor values. If the two resistors are too small, then they will draw too much current from VDD when the LVCMOS output is high. If the resistor values are too large, then the input RC time constant might limit LVCMOS slew rate.

    In general, 100 ~ 1000 Ohm should be fine.

    Regards,
    Hao

  • 0 in reply to Hao Z
    TI__Intellectual 1480 points

    Hi Hao-san,

    Thank you for your answer!

    Understood. I'm going to recommend the resistor value @100~1000ohm to the customer.

    Best Regards,

    Kazuki Kitajima