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LMX2572: Reference clock

Gregory Duperon
Expert 7470 points
Part Number: LMX2572

The datasheet makes a statement that "In general, the best performance is for a high slew rate but a lower amplitude signal, such as LVDS." How much of a difference does the amplitude make?

I'm using a buffer to drive the clock to it which is available with both LVDS and LVPECL outputs, but this presents a conundrum as the LVDS flavor of the part has worse jitter performance than the LVPECL. Without knowing how the LMX2572 reacts, I have no way to quantify what would give me better system performance (short of putting together some EVMs in the lab, but that's not really feasible).

Is there any data available that might quantify the "lower amplitude" statement? The LVPECL version of my buffer is about 90fs jitter 12k-20MHz (for my 100MHz reference), while the LVDS version is 107fs. While not a gigantic difference, it still is 17%. Given my loop bandwidth, the higher part of that curve doesn't matter, but the ~6dB differences from 10Hz to 1kHz offsets does.

  • 0
    TI__Guru** 108130 points

    Hi Gregory,

    Let say we have two ref clocks (say 10MHz), they have the same phase noise (not jitter but phase noise) and amplitude. One of them is sine wave and the other is square wave. The PLL phase noise will be better if we use the square wave ref clock. This is because the slew rate is much better with the square wave clock.

    If we vary the amplitude of the square wave clock, I think we may not see noticeable phase noise difference from the PLL. The ref clock amplitude is not matter here. However, if the ref clock is a sine wave, then you will get a better phase noise with a higher amplitude ref clock. this is because the slew rate of the ref clock is getting better with a higher amplitude. This is true when the ref clock freq is small. At higher ref clock frequency, for example, 100MHz, we will not get much slew rate improvement with a higher amplitude setting.

    Another example, if we have two ref clocks, same freq, same amplitude and slew rate but different phase noise, the PLL phase noise will also be different. The difference will depend on the loop bandwidth and the ref clock phase noise profile. If your design concerns phase noise at 10Hz to 1kHz, then the phase noise of the ref clock at these offset frequencies should be good. The ref clock jitters you've measured were specified at 12k-20MHz offsets, you don't know what happen at 10Hz - 1kHz offsets.