• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 22 subscribers
  • Views 746 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04821: Baseline DCLK / SYSREF Phase Offset After SYNC Event and Without Additional Delays

dtaylor
Prodigy 130 points

Part Number: LMK04821

Hi,

we have an application using the LMK04821 for JESD204B device clock / continuous SYSREF generation in subclass 1 mode. We have followed the approach given in the datasheet for achieving a determistic phase relationship between DCLK and SDCLK and are now in the process of coarse-tuning the various digital delays in both paths in order to meet sample/hold timings. The first six output groups are connected to the JESD converters and an FPGA while we have a scope attached to the last output group. The SYSREF divider is an integer multiple of all DCLK dividers.

When all delays are disabled/powered down, we would expect to see DCLK and SDCLK edge-aligned (due to the integer multiples), maybe with ~50ps skew. There is, however, a large (but, after the SYNC event, deterministic) phase offset between the rising edges of the DCLK and SDCLK outputs which also seems to depend on the DCLK divider value. Is this expected behavior? I.e. should we use the probed output group to adjust the delays until sample/hold times are met on the scope allowing for a safety margin of ~100 ps and then transfer the respective settings to the clock groups 1-6 connected to the other devices?

Thank you and best regards
David

  • 0
    TI__Mastermind 35440 points

    Hello David,

    I would expect the delay behavior to depend on the SYSREF divider value, moreso than the DCLK divider value. The settings for one group should be equivalent for all groups configured identically.

    This picture should help clarify the relationship between DCLK delay and SYSREF delay:

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 130 points

    Hello Derek,

    thank you very much for your answer, the picture you provided indeed clarifies the timing.

    Maybe it is a good idea to include a similar figure in a future version of the datasheet? I think your explanation regarding ts and the two ADJUST values is much clearer than what is currently written there.

    Thanks again and best regards
    David