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Original question:

LMK04832EVM: Can not setup LMK04832 operate in Dual Loop mode

LMK04832: RFSOC LMK04832 -> LMX2594 Clock Output Jitter

Alexander Scott
Prodigy 20 points
Part Number: LMK04832
Other Parts Discussed in Thread: LMX2594,

It appears I am using the same board (based on the schematic screenshot in the referenced post) and am unable to use dual loop mode.  It appears we have significant Jitter on our RFSOC DAC output, which we believe to be related to the reference clocks.  

This part is being configured in single loop mode as in the attached tics file.  

Additionally this part feeds a pair of LMX2594 devices which is then used to provide a 3.93216 GHz reference clock to the RFSOC DAC tiles.  The configuration tics file of these devices is also attached.  

Are there any suggestions to our configuration to improve clock jitter performance?  Unfortunately we are unable to revise/rework 3rd party circuit board to include the mentioned .1uF Cap on the OSC_N pin.  

Thankslmk04832.tcslmx2594.tcs

  • 0
    TI__Mastermind 33430 points

    Hello Alexander,

    The LMK04832 PLL2 input is connected to CLKin1 in the tcs file. The schematic in the linked post shows a 0.1µF to GND on CLKin1. If your configuration is taking 122.88 MHz in from CLKin1, and the schematic is the same as in the linked post, I don't think you would be having issues from input configuration.

    In the file you sent, there is a continuous SYSREF active at 7.68 MHz. Also, the format for most of the SYSREF outputs is CMOS (Norm/Norm). This single-ended signal will crosstalk significantly with the device clocks and is likely a large source of noise in your application, since 7.68 MHz is an in-band spur for most 12k-20M data converters. If there is a way to check application performance with SYSREF in pulsed mode or off altogether, I recommend checking this first. If the SYSREF must be continuous, is it possible to put the CMOS signals in differential mode (Norm/Inverted)? This could help a small amount.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 20 points

    Hi Derek,

    Thank you for reviewing the TICS files.  

    We are using CLKin1 directly into PLL2 and have observed the DLD lock indicator LED on our board.  I was referencing the other post as to why we are unable to use Dual Loop Configuration to improve Jitter Performance.   

    I have disabled the CMOS NORM/NORM SYSREF outputs and have not seen any improvement to the jitter issue we are seeing on the DAC output.  

    Do you have any other suggestions to try? 

    Thanks,


    Alex

  • 0 in reply to Alexander Scott
    TI__Mastermind 33430 points

    Hi Alex,

    I did see that your PLL1_NCLK_MUX state is set to a reserved value, which could be causing some interference on the PLL2_NCLK_MUX signal. You could try setting this to an allowable value.

    Apart from that, I did not see anything that would suggest why your jitter values are increased. As an experiment, you could try removing the VCXO signal, disabling PLL1, and placing a clean clock in from CLKin1 to PLL2. Depending on the frequency used (122.88 MHz or 2949.12 MHz), you would be able to determine at which stage the noise issues are appearing.

    Regards,