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LMK04828: LMK04828 used to distribute DCLK and SYSREF (SCLK) configuration problem

gang huang
Prodigy 230 points
Part Number: LMK04828

Hi, 

I am using a 4DSP FMC120 board have LMK04828 as clock distribution. 

Now I am trying to sync multiple this board by a external clock and sysref generator. 

From the external clock and sysref generator, I generate 1G and 1G/256=3.9M signal connected to clock 1 (1G) and clock 0 (3.9M) of the LMK04828.

I use the attached registers (config1_output2_122M.txt) setting give me strange output on output 2, which should be 1G/4=250M but I got 122M, while the output 3 seems right which gave me the 3.9M from clock 0

If I then disable the sync_en as (config1_output2_252M.txt) and then of course I don't have the output 3 which should come from sysref. 

How should I setup the chip to get the output 2 at 250M (clkin1/4) and output 3 at 3.9M (clkin0)?

Thanks,

  • 0
    Prodigy 230 points

    sorry, forgot the attachments.

    Fullscreen config1_output2_122M.txt Download 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010061
R257	0x010122
R258	0x010255
R259	0x010302
R260	0x010420
R261	0x010500
R262	0x0106f0
R263	0x010755
R264	0x010864
R265	0x010922
R266	0x010A55
R267	0x010b05
R268	0x010C20
R269	0x010d00
R270	0x010eb0
R271	0x010f11
R272	0x011061
R273	0x011122
R274	0x011255
R275	0x011302
R276	0x011420
R277	0x011500
R278	0x0116f0
R279	0x011757
R280	0x011861
R281	0x011922
R282	0x011A55
R283	0x011b02
R284	0x011C20
R285	0x011d00
R286	0x011ef0
R287	0x011f57
R288	0x012062
R289	0x012122
R290	0x012255
R291	0x012305
R292	0x012420
R293	0x012500
R294	0x0126B0
R295	0x012711
R296	0x012862
R297	0x012922
R298	0x012A55
R299	0x012b02
R300	0x012C20
R301	0x012d00
R302	0x012ef7
R303	0x012f00
R304	0x013061
R305	0x013155
R306	0x013255
R307	0x013302
R308	0x013420
R309	0x013500
R310	0x0136f7
R311	0x013700
R312	0x013840
R313	0x013905
R314	0x013a01
R315	0x013b00
R316	0x013c00
R317	0x013d08
R318	0x013e00
R319	0x013f00
R320	0x0140F3
R321	0x014100
R322	0x014200
R323	0x014310
R324	0x014400
R325	0x01457f
R326	0x014618
R327	0x014790
R328	0x014800
R329	0x014900
R330	0x014a00
R331	0x014b05
R332	0x014cff
R333	0x014d00
R334	0x014e00
R335	0x014f7f
R336	0x015000
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x016244
R355	0x016300
R356	0x016400
R357	0x01650C
R369	0x0171aa
R370	0x017202
R380	0x017c15
R381	0x017d33
R358	0x016600
R359	0x016700
R360	0x01680C
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017360
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53
    Fullscreen config1_output2_252M.txt Download 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010061
R257	0x010122
R258	0x010255
R259	0x010302
R260	0x010420
R261	0x010500
R262	0x0106f0
R263	0x010755
R264	0x010864
R265	0x010922
R266	0x010A55
R267	0x010b05
R268	0x010C20
R269	0x010d00
R270	0x010eb0
R271	0x010f11
R272	0x011061
R273	0x011122
R274	0x011255
R275	0x011302
R276	0x011420
R277	0x011500
R278	0x0116f0
R279	0x011757
R280	0x011861
R281	0x011922
R282	0x011A55
R283	0x011b02
R284	0x011C20
R285	0x011d00
R286	0x011ef0
R287	0x011f57
R288	0x012062
R289	0x012122
R290	0x012255
R291	0x012305
R292	0x012420
R293	0x012500
R294	0x0126B0
R295	0x012711
R296	0x012862
R297	0x012922
R298	0x012A55
R299	0x012b02
R300	0x012C20
R301	0x012d00
R302	0x012ef7
R303	0x012f00
R304	0x013061
R305	0x013155
R306	0x013255
R307	0x013302
R308	0x013420
R309	0x013500
R310	0x0136f7
R311	0x013700
R312	0x013840
R313	0x013905
R314	0x013a01
R315	0x013b00
R316	0x013c00
R317	0x013d08
R318	0x013e00
R319	0x013f00
R320	0x0140F3
R321	0x014100
R322	0x014200
R323	0x014300
R324	0x014400
R325	0x01457f
R326	0x014618
R327	0x014790
R328	0x014800
R329	0x014900
R330	0x014a00
R331	0x014b05
R332	0x014cff
R333	0x014d00
R334	0x014e00
R335	0x014f7f
R336	0x015000
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x016244
R355	0x016300
R356	0x016400
R357	0x01650C
R369	0x0171aa
R370	0x017202
R380	0x017c15
R381	0x017d33
R358	0x016600
R359	0x016700
R360	0x01680C
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017360
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

  • 0 in reply to gang huang
    TI__Mastermind 33710 points

    Hello Gang,

    In your first configuration (config1_output2_122M.txt), you have written 0x144 = 0x00. These are the SYNC_DISx bits, and they gate the output divider resets from the shared SYNC/SYSREF Distribution Path. With 0x144 = 0x00, a divider reset on the outputs is issued with every reclocked edge of the CLKin0 input. I believe if you set 0x144 = 0xFF, you should see the expected results.

    Regards,