LMX2572LP: LMX2572LP best software for design and simulation.

Noel Fung said:

Hi mike,

TICS Pro can help you setup your configuration and generate all the register values. Some registers have critical restriction, this tool will alert you if you have violated the restriction. You could also mouse-over the boxes to see the description of that register.

PLL Sim is a design tool, you will need this tool to design the loop filter, check the phase noise and spurs.

For DMR application, I think LMX2572LP is the best choice. The lowest power consumption synthesizers we have is the LMX2531 series, but they are narrow band devices, you may need several parts to support all the frequencies you want.

Again for DMR application, you will need to use TCXO, so the output format is never LVDS. In order to get better PLL noise, I suggest use as highest frequency as possible. Higher frequency returns higher slew rate, this could compensate the slew rate loss in clipped-sine wave format.

Hi Noel,

Thanks, will take a look at the software in due time. But just a question regarding the initial tuning and the loop filter. These settings are set-up once at boot-time and then will not require any further adjustment regardless of the frequency tuned, or will some adjustment be required during the use of the synthesizer. The reason I'm asking is that it is intended for an application that includes FHSS hopping at say 50ms intervals...

With regards to the TCXOs we have come across some devices from Abracon, the ASGTX5 Series of XOs that do come with an LVDS output option besides PECL or HCSL etc , and also meet Stratum 4 requirements. Their designed with a 100 Ohm differential load in mind, and with a typical 300mVp-p output. I think these might be OK for the LMX2572 ? Any thoughts on the suitability of these devices for the LMX2572  ?

Also, I notice the highest clock input frequency is 250MHz without the doubler. What is better using the doubler, or bypassing it and going straight in with say a 200MHz differential output XO ??

Regards, mm

Noel Fung said:

Hi Mike,

The ASGTX5 is a XO, not TCXO, are you sure you can use it in DMR application? DMR is a narrow band system and it has quite tight frequency accuracy spec.

Since there are many channel in a certain DMR band, you may need to adjust some of the loop parameters in order to meed spurs and phase noise requirement. 

The doubler does not add noise, but it is required only when the input clock frequency is low. For example, if the input clock is just 20MHz, then I would suggest use the doubler to make fpd = 40MHz. This will reduce the N-divider value and therefore reduce PLL noise.

Hi Noel,

The application is proprietary DMR in the ISM bands and not subject to the same standards and classic requirements. 50 KHz channel separation can accommodate more relaxed specifications on frequency stability, however given that, I notice that Abracon also have the ASGTX-D series of TCXO, albeit x2 more expensive. It could be a contender ...

With regards to the adjustment of loop parameters, can the software simulator be used as a good enough guide to the final expected spurs and phase noise resulting with the change of one channel to another (assuming all other factors such as board layout etc meet the performance required for the LMX2572) ? What are the parameters that generally need to be tweaked to obtain such fine adjustments that you refer to ?

To some extent the stringent channel separation issue is not as severe in the proprietary application we are considering where 50KHz up to 100 KHz separation is acceptable. Close-in spurs and phase noise requirements could be more relaxed due to the wider channel separation possible.

Ok for the doubler, if it’s bypassed, I guess using a 100 – 200 MHz LVDS oscillator with 2 - 3ppm will meet the requirements.

Thanks in advance.