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CDC3RL02: datasheet description about input impedance

Gene Qiu
Intellectual 1720 points
Part Number: CDC3RL02
Other Parts Discussed in Thread: LMH2191TMEVAL, LMH2191

Hi team,

Customer wants to use two clock buffer cdc3rl02 cascades to output three channel clock signals, but has concern that the voltage range may not enough, there are several questions about the usage need your help me to double confirm, thank you!

1. Check whether the output waveform voltage amplitude and input amplitude of cdc3rl02 are the same, from the graphic display of the specification on datasheet it is the same?

2. I / O impedance problem. The input impedance of cdc3rl02 in the specification is 6K / / 4.75pf, and the output load seems to require CL = 10-50pf?

When cascading, does the output of the front buffer need to match the input impedance of the back buffer? Also, does the load impedance need to match? any suggestion

3. If I want to connect a 5th order LC filter network at the clock output stage to suppress harmonics. Can I simulate the LC value according to the input and output impedance like 50R?

Best Regards,

Gene

  • 0
    TI__Genius 16845 points

    Hi Gene,

    A1. Output amplitude will depend on the load. I observed ~1.05V swing when loaded with 50ohms to GND.

    A2. 10-pF to 50-pF load is mentioned in the datasheet because adding some small load capacitance will reduce the output slew rate which benefits EMI.

    Impedance matching is always recommended when designing for high speeds as it improves signal integrity. This would be matching the driver's impedance (plus any series components) to the impedance of the trace and to the impedance seen by the receiver.

    However LVCMOS output drivers typically expect to drive a high impedance so there shouldn't be an issue with a direct connection of the output or input (if driving from an LVCMOS source)

    A3. I would highly recommend to evaluate CDC3RL02 in the lab, you can use LMH2191TMEVAL board and replace the LMH2191 with CDC3RL02. I personally haven't tried using a complex filter on the output before but it shouldn't be a major issue. Let me gives you some tips for designing:

    When designing for lowest jitter, it is recommended to use impedance matching for best signal integrity. This is 50ohm impedance at DC, which means zero reactance and all resistance. When using load capacitance for improved EMI, you would be trading off jitter performance for EMI performance. When designing your filter, it may not work as desired if you are also forced to limit the reactance. I'm interesting in seeing how you will proceed and the result.

    Kind regards,
    Lane