LMK05028: PLL during holdover

Hello, 

What is meant by system clock here? When references are gone DPLL goes into holdover however the APLL should remained locked. The APLL is using an XO probably and as long as APLL is locked the outputs will remain functioning properly. 

Amin 

Amin,

System clocks generated via TXCO/OCXO and XO sources.

Is 3 loop configuration being used? Is a TCXO being used for TCXO DPLL and XO for APLL? 

It is not recommended that the APLL reference (assuming XO is being used) disappear under any circumstance, there's no APLL holdover. Outputs with 100% be impacted. 

With regards to TCXO, what specifically is the glitch? Depending on level, duration, etc. different impact may be observed, need details of glitch. 

Amin 

Hi Amin,

We’d prefer to use 2-loop mode to avoid putting an extra crystal down.

What we need to do:

-          Take in a super stable oscillator (we are using a 5ppb OCXO or better) for the system clock.

-          Take in a 1PPS reference from a GPS unit.

-          Output phase aligned:

• 1PPS (what we are currently testing)
• 10MHz (future)
• 20MHz (future)
• 25MHz (future)

-          Output optional:

• 27MHz (HDMI)
• 156.25MHz (Ethernet)

We need the part to keep frequency and phase (phase at least for the 1PPS) when the 1PPS reference input is lost.

How do we set this up?

What we think the setup needs:

2-loop and use the 5ppb clock (either 10MHz or 50MHz?) feeding the XO input, disconnect the TCXO port.

Feeding in a 1PPS on the IN1 port (just where we have connected the reference).

We have used the 5V input on V1.

Can we set up a 0-phase 1PPS output with lost reference holdover using this?

We can’t seem to get the 0-phase running. Can you send us a TICS Pro file to help us set this up?

Cheers,

   Shawn

Hi guys,

We have had some luck getting the part to synchronize to references over 1KHz, but not below that. Unfortunately my PM waits for no one and without a valid setup, we will be forced to use the AD9454 part which we do have working.

I would love to be able to present a TI solution as well for evaluation, but so far cannot get this running. Any ideas to configure this properly?

Cheers,

    Shawn

Hi Shawn, 

So to summarize you currently have a working config for 1 kHz however this doesn't work when you go to 1 Hz? Presumably all you're changing is updating the main start page for IN1 (I believe that's the input you mentioned you're using) to be 1 rather than 1e3. 

I'm assuming the source into IN1 is remaining the same, with regards to amplitude, slew rate, etc. outside of just updating the frequency. 

Are the issues with DPLL frequency / phase lock or the reference is not even being validated? 

Just an overview, which you may already know, but if not this can be useful. On TICSpro status tab, you can read status registers and there it will show you whether REF is valid and secondly whether DPLL has achieved frequency and phase lock. 

For DPLL to lock the REF needs to be valid first, if no reference is valid no DPLL lock. DPLL lock can be confirmed by monitor R div and N div on the status channels, and when those signals are in phase or 180 deg phase shifted then DPLL has fully locked. 

With regards to the 1 pps signal, if its not valid can you change the input validations and see if that allows the input to become valid? Does the DPLL lock then? Please allow some time for this happen, it will not be immediate. By observing R div / N div on the status channel you can gauge whether it's getting close to locking or not. 

Below i have some pictures of what's mentioned above. 

Regards, Amin 

Status to read back DPLL frequency and phase lock 

Reference Valid readback on status 

Disable Validation Timer, PPM detect, and Missing Clock (both missing and runt) 

Confirm only Amplitude detect is enabled for references on User Control tab

Program Status 0/1 or GPIO 5/6 as R div - N div signals from DPLLx and monitor - in phase or 180 phase shifted to confirm lock - can monitor and observe whether DPLL is trying to lock or it's getting stuck 

Hi Amin,

The device does lock, but at an indeterminate phase. I do require 1PPS phase alignment on the output.

Can you send me the TICs Pro setup file for what you are describing?