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LMK01801: Current Consumption clarifications

Binayak Shrestha88
Expert 1520 points
Part Number: LMK01801


Hi,

We are using LMK01801 in our design. It has two differential input clocks as well as four LVDS output clocks:

- CLKIN0_P/N
- CLKIN1_P/N

- CLKOUT0_P/N
- CLKOUT5_P/N
- CLKOUT9_P/N
- CLKOUT12_P/N

Table 9-1 in the datasheet shows Typical Current Consumption for selected functional blocks (snapshot attached).

Based on the table, I've done current consumption calculation and the related doubts that I have are as follows:

1. Core current = 1mA

2. Bank A current = 22mA x 2 clkouts (clkouts: 0 and 5) + 22mA (CLKIN0) = 44mA + 22mA = 66mA
   -- or should it be
   Bank A current = 22mA (clkouts 0 and 5; clkin0)= 22mA
 
3. Bank B current = 25mA x 2 clkouts (clkouts: 9 and 12) + 25mA (CLKIN1) = 50mA + 25mA = 75mA
   -- or should it be
   Bank B current = 25mA (clkouts: 9 and 12; CLKIN1) = 25mA

4. Buffers = 15mA (CLKOUT0) + 15mA (CLKOUT5) + 15mA (CLKOUT9) + 15mA (CLKOUT12) = 60mA

5. Output divider = 24.2mA (CLKOUT0) + 24.2mA (CLKOUT5) + 24.2mA (CLKOUT9) + 19.1mA (CLKOUT12) = 91.7mA  
   -- or should it be
   Output divider = 24.2mA (CLKOUT0 to CLKOUT11) + 19.1mA (CLKOUT12 to CLKOUT13) = 43.3mA

6. Input Dividers = 9mA (Bank A) + 9 mA (Bank B) = 18mA

7. Analog Delay = 2.8mA (for CLKOUT12) = 2.8mA

8. LVDS clock output buffers = 9mA (CLKOUT0) + 9mA (CLKOUT5) + 9mA (CLKOUT9) + 14mA (CLKOUT12) = 41mA



Kindly let me know if my calculations are correct along with some doubts presented in points 2, 3, and 5.

Regards,

Binayak

  • 0
    TI__Expert 6140 points

    Hello Binayak, 

    I'll follow the same pattern you have: 

    1. Does not apply, since condition states all outputs and dividers are off (this would be similar to a power down condition) which is not the case. 

    2. Bank A: 22 mA. Not per output calculation. This is essentially a minimum for bank A. The add-ons come with the next stages. 

    3. Bank B: 25 mA. Not per output calculation. This is essentially a minimum for bank B. The add-ons come with the next stages. 

    4. Buffer: correct. 15 + 15 + 15 + 15 = 60 mA 

    5. Output dividers: If you look on page 2 of the datasheet, the block diagram shows there are 4 output dividers, GC1, GC2, GC3, and GC4. Since outputs 0, 5, 9, and 12 are being used, each output divider is being used. Therefore the calculation should be: 

    24.2 + 24.2 + 24.2 + 19.1 = 91.7 mA 

    6/7/8: are correct. 

  • 0 in reply to Amin Eshraghi
    Expert 1520 points

    Hi Amin,

    Thanks for clearing things out. Based on above reply and your reply from my other thread regarding current consumption per power pin (e2e.ti.com/.../3289131), I've tried to map out how much current is consumed by each power pin in my configuration.

    1. VCC2_CLKIN0 = 22mA (Bank A) + 9mA (input divider for Bank A) = 31mA

    2. VCC6_CLKIN1 = 25mA (Bank B) + 9mA (input divider for Bank B) = 34mA

    3. VCC1_CLKOUT0_1_2_3 = 24.2mA (O/P divider CG1) + 15mA (Buffer) + 9mA (O/P LVDS buffer for CLKOUT0) = 48.2mA

    4. VCC3_CLKOUT4_5_6_7 = 24.2mA (O/P divider CG2) + 15mA (Buffer) + 9mA (O/P LVDS buffer for CLKOUT5) = 48.2mA

    5. VCC5_CLKOUT8_9_10_11 = 24.2mA (O/P divider CG3) + 15mA (Buffer) + 9mA (O/P LVDS buffer for CLKOUT9) = 48.2mA

    6. VCC7_CLKOUT12_13 = 19.1mA (O/P divider CG4) + 15mA (Buffer) + 2.8mA (analog delay) + 14mA (O/P LVDS buffer for CLKOUT12) = 50.9mA

    Are the above calculations correct?

    From both the threads (this thread and my other thread mentioned intitially), I'm not able to find out how much current is consumed by the following pins:

    [a] VCC8_DIG
    [b] VCC4_BIAS

    In addition, what are the purpose of these two pins (since these two power pins don't come into picture of supplying current as per our discussions as of now)?

    Thanks and Regards,
    Binayak

  • 0 in reply to Binayak Shrestha88
    TI__Expert 6140 points

    Hi Binayak, 

    I think your calculations above are reasonable, but please do note that these are typical numbers, so there will be some variance. 

    Vdd8_dig pin probably sets the power on reset and allows the device to power up correct. Presumably the current consumption will be minimal, I'm inclined to go with the 1 mA number both in power down and on table 9-1 for core. This may be slightly higher in powered up condition, but it will still be significantly smaller compared to other supply pins. 

    Vcc4_bias optimizes device performance: 

     

    Regards, Amin

  • 0 in reply to Amin Eshraghi
    Expert 1520 points

    Hi Amin,

    Thanks for the clarification.

    One point that was not mentioned was how much current VCC4_BIAS is consuming. I'm guessing it is negligible (few milli-amps only) compared to other rails. Am I correct?

     

    Thanks and Regards,

    Binayak

  • 0 in reply to Binayak Shrestha88
    TI__Expert 6140 points

    Hi Binayak, 

    I agree with your assumption, specially since we considered the conditions laid out in table 5.4 for typical and max Icc with all channels in LVDS mode and calculated a per block total using table 9.1 in the other thread. I anticipate very low current on Vcc4_Bias similar to Vcc_dig. 

    Regards,

    Amin

  • 0 in reply to Amin Eshraghi
    Expert 1520 points

    Hi Amin,

     

    Thanks alot. You were of great help!

     

    Best Regards,

    Binayak