• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 3 answers
  • Subscribers 22 subscribers
  • Views 723 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04828: Phase noise degradation in clock distribution usage?

Toshihiro Watanabe
Genius 10235 points
Part Number: LMK04828
Other Parts Discussed in Thread: LMX2582, , LMK05318, LMK03318

Hello,

The customer need fractional PLL and 8 output clock. Phase noise performance can almost meet the requirement by using LMX2582 but it has two output.

I think LMK04828 can be used as clock distribution and divider so I thought LMK04828 can be used for low noise clock buffer.

 Fin pin -> CLOCKin1 OUT MUX select Fin -> VCO MUX select Fin -> clock distribution

The customer needs 1/1, 1/2, 1/10 divider.

I think LMK04828 is used for high speed ADC clock distribution in this mode often. I guess phase noise degradation would be small.

Can LMK04828 use for low noise clock distribution device?

Best regards,

Toshihiro Watanabe  

  • 0
    TI__Genius 12705 points

    Hello Toshihiro,

    Yes, the LMK04828 can be used for distribution mode, this is a common use case for fanout ADC clocks as you mention. 

    You may also want to consider one of our 8 output clock generators if they have sufficient noise and frequency output range capability such as LMK03318. LMK05318 can also be configured as clock generator.

    Regards,

  • 0 in reply to Liam Keese
    TI__Genius 10235 points

    Hello Liam-san,

    Do we think no issue reference clock p\\\\\\\\\\\\\\hase noise copies to output clock when LMK04828 uses clock distribusiton mode?

    I am interesting in LMK05318 but i don't know how to simulate the performance. PLLatinum has an option for LMK05318 but it seems APLL. LMK05318 is DLL.

    Could you teach us how to simulate LMK05318 by PLLatinum?

    So far, LMX2582 almost meet the spec however 1kHz and 10kHz offset phase noise are severe. Other PLLs does not meet the spec. I guess VCO phase noise affects the performance since LMX2582 VCO phase noise is low.

    This is why I consider LMX2582 + LMK04828 clock distribution mode configuration. If we can know LMK05318 has enough phase noise performance by simulation, LMK05318 will be better solution.

    Best regards,

    Toshihiro Watanabe

  • 0 in reply to Toshihiro Watanabe
    TI__Genius 12705 points

    Hello Toshihiro,

    The noise for the > 1 kHz range  will track the performance of the APLL and BVCO as the loop bandwidth of the DPLL is very narrow. I would expect the Pllatinum sim to provide accurate prediction until < 100 Hz.  Noise at 10kHz is extremely good. 

    Adding the DPLL to calculation for Pllatinum Sim would require some significant changes which are not currently planned..

    Please see this post for more discussion on additive noise in distribution mode.

    e2e.ti.com/.../3286076 distribution#3286076

    Regards,

  • 0 in reply to Liam Keese
    TI__Genius 10235 points

    Hello Liam-san,

    Please let me ask you about PLLatinum simulation.

    We can get accurate result by PLLatinum in >100Hz range if DPLL BW is very low.

    LMK05318 DLL goes to APLL N divider. APLL VCO range is very small. From this, we need to use APLL2 with cascade mode if we need fractional relationship between reference clock and output clock. Because APLL2 has wider VCO range.

    Is my understanding, APLL2 with cascade mode is needed, correct?

    If correct, I think we need to simulate twice, in case of APLL1 and in case of APLL2.

    Could you share me simulation file which PLLatinum can load?

    I tried it but it seems not work properly. I would like to modify setting from the simulation file.

    Input reference clock frequency is 10MHz, output clock frequency is 200.1MHz for instance. 

    Best regards,

    Toshihiro Watanabe

  • 0 in reply to Toshihiro Watanabe
    TI__Mastermind 18070 points

    Hi Toshihiro-san,

    Yes if the VCO is not 5GHz then PLL2 is needed. For cascaded PLL1 and PLL2 simulation, you need to first select PLL1, design the loop filter and export the phase noise trace (data export -> export trace -> phase noise total). Then switch to APLL2 and import the data for OSCin

    Regards,
    Hao