Other Parts Discussed in Thread: LMK04832
Hello.
In my system, I am driving several LMK04828 Devices using a single LMK04832 in JESD204b configuration.
I supply a 1.2GHz, LVPECL1.6 clock from DCLKOUTx of the LMK04832 to clkin1 of the LMK04828,
and a single sysref pulse from SDCLKOUTx (of the LMK04832 ) to clkin0 of the LMK04828. (also using LVPECL1.6)
The 1.2GHz clock is generated using a 10MHz reference and a 100MHz TCXO, and it's second phase detector is running on 100MHz.
The second PLL of the LMK04832 generates 100MHz spurious signals around the 1.2GHz carrier that are attenuated -80dbc.
next, the clkin1 1.2GHz signal in the LMK04828 is directly buffered and sent to an ADC.
when I measure the output of this buffered clock, I see that the 100MHz spurious signals are now -60dbc and not -80dBc from the carrier, and this impacts my ADC performance.
I have tried to use the doubler and send these spurious signals to 200MHz or even 300MHz away, but in either case, this may impact my system's performance.
I forgot to mention that all of the clock signals are routed deferentially, and this situation was repeated using the LMK's EVBs.
Is there a way to cause the LMK04828 to suppress these signals? ( my intention was to use it only for clock division and distribution). if it may help, I can replace it with an LMK04832 as well.
Thank you for helping during the Corona crisis
Itamar Mazaki
