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LMK04828: how to generate 148.4375 using 100 MHz crystal connected

Rajesh khanna
Intellectual 700 points
Part Number: LMK04828
Other Parts Discussed in Thread: LMK04832

Hi,

I need to generate 148.4375 as reference clock to FPGA from lmk04828.

can you please give settings for this frequency in tics pro.

Regards,

Rajesh khanna

  • 0
    Intellectual 700 points

    HI,

    The frequency in 148.4375 MHz.

    Regards,

    Rajesh khanna

  • 0 in reply to Rajesh khanna
    TI__Mastermind 33340 points

    Hi Rajesh,

    First, TICS Pro has a frequency planner tool available for the LMK04832 (P2P part which has approximately the same VCO ranges as LMK04828). You could use the LMK04832 frequency planner in TICS Pro, find a solution you like, and copy the R-divider and N-divider settings to achieve the same results in the LMK04828.

    Please try the frequency planner on your own first. If you still need assistance after that, at least provide the input frequency, the planned usage mode (dual-PLL jitter cleaner, single-PLL clock generator, distribution mode buffer), and the desired VCXO frequency if used.

    Regards,

  • 0 in reply to Derek Payne
    Intellectual 700 points

    HI Derek,

    Thanks for your comment, i am not able to find frequency planner in tics pro.

    input frequency = PLL 1 --> 10 MHz

    the planned usage mode (dual-PLL jitter cleaner, single-PLL clock generator, distribution mode buffer) ==> dual-PLL jitter cleaner, 

    desired VCXO frequency ---> 100 MHz

    Required frequency ---> 148.4375 MHz

    Regards,

    Rajesh khanna

  • 0 in reply to Rajesh khanna
    TI__Mastermind 33340 points

    Hello Rajesh,

    Sorry you couldn't find the frequency planner. I'll double-check that it was included in our latest release, this is one of a few cases in the last few days we've noticed people could not find features that should be released, so we're looking into it.

    Thanks for providing the desired inputs. There are a few options which could work with 100 MHz VCXO, but the best one I'm seeing is to set PLL1 phase detector to 10 MHz, PLL2 phase detector to 1.25 MHz, and run PLL2 VCO at 2968.75 MHz. The clock output divide would be 20. Note that running the PLL2 phase detector at this low frequency is not ideal for the best performance, since it will restrict the loop bandwidth and elevate PLL2 noise. But if the phase noise is not too critical, this approach could work.

    On the other hand, a 156.25 MHz VCXO would work very well: it takes advantage of PLL1 as a jitter-cleaner and transitions from the 10MHz reference to a more suitable common divisor with the desired output frequency, while maintaining a higher PLL2 phase detector rate and achieving better phase noise performance. With 156.25 MHz VCXO, PLL1 phase detector would be 1.25 MHz, and PLL2 phase detector would be 78.125 MHz. The PLL2 VCO frequency would still be 2968.75 MHz.

    Regards,