Other Parts Discussed in Thread: USB2ANY
Hi all
Would you mind if we ask LMK03328?
Our customer has some trouble in case of EEPROM write using FPGA.
They confirmed that they could write all of data to SRAM.
However, they seems that they couldn't copy all of data from SRAM to EEPROM.
And then, if they use USB2Any with code loader, there is no problem.
<The customer's procedure of the data copy from SRAM to EEPROM >
1. Write 0xEA to R144. This provides basic protection from inadvertent programming of EEPROM.
2. Write a 1 to R137.0
3. Write 0x00 to R144
4. Read R137 BIT5=0 and BIT2=0
<Question1>
The interval between 1. R144 write, 2. R137 write and 3. R144 write are each 5ms.
Is there any rule(limitation) at each interval?
<Question2>
The result of R136 register was follows;
In case of USB2ANY : 0x9A
In case of FPGA(Customer's procedure) : 0x9D
What does this indicate?
<Question3>
They confirmed the SRAM data also.
There is the difference at BYTE4's register(NVMSCRC).
In case of USB2ANY : 0x00
In case of FPGA(Customer's procedure) : 0x0C
Could you give us some advice?
Kind regards,
Hirotaka Matsumoto