SSTE32882 Operation in Mirror Mode

I'm using two SSTE32882 DDR3 Registers.  One is in normal mode, the other is in Mirror Mode (Mirror bit high).  QuadCSEN# is set low for quad chip select enabled.  I'm in the processing of bringing up first protos.  Thus far, the register in normal mode is 100% functional.  CS0 & CS2 accesses work (CS1 & CS3 are not supported yet).  The register in Mirror mode is not as functional.  Thus far, CS0 is functional, but accesses through CS2 fail.  When the device is brought out of reset, CS0 is high, CS1 is high, CS2 is low, and CS3 is high.  Thus far, I've tested accesses through CS0 and they work as expected.  Accesses through CS2 do not work.  CS1 & CS3 are associated with rank 2 which is not yet supported (i.e., the DRAM on the protos are single rank).  Has anybody experienced similar behavior with this register?  I haven't found any information in the specification that would explain CS2 ever defaulting to a low state given that the input is being held high.  Any help is appreciated.