LMX2572: Lock time with full assist mode at VCO core boundary

Hi There,

I think you can set VCO_SEL_FORCE=1 and set VCO_SEL to the desired VCO core during initial VCO calibration. The chip will calibrate using only this VCO core and find the VCO_CAPCTRL and VCO_DACISET to you. 

Hello Noel,

thanks for your quick answer. We will give it a try. I will report the findings.

Hello

Forcing calibration to use the VCO of the neighboring band by writing VCO_SEL and setting VCO_SEL_FORCE=1 worked. There is actually considerable overlap of VCO frequency ranges, i.e. VCO4 calibrates fine up to 5380 MHz, while VCO5 calibrates fine above 5060 MHz. With "calibrated fine" I mean that the resulting VCO tuning voltage is within 1.3 to 1.4 V.

However, using the VCO of the neighboring band did not solve the initial problem of long lock time at certain frequency sweep points.

During the investigation I made the following new observation: The lock time is only increased when N crosses from <259 to >=259.

For example the (non-monotonic) frequency scan with N = 257 258 259 260 261 260 259 258 257 will result in long lock time at the first occurrence of N = 259, but not at the second. The other registers needed for fast assist are also changed accordingly but not listed here.

Another example: The scan with N = 255 256 273 274 273 274 273 274 255 256 will result in long lock time at the first occurrence of N = 273, but not at the following occurrences of N = 273 or any other points.

I will test for larger ranges of N to see if there are other critical values for N.

Do you have any explanation for this behavior?

Hi Websurfer,

Please also provide the VCO_DACISET value. The longer lock time might due to a big DACISET jump. 

Hello Noel

Here are the values of the PLL and VCO parameters of the sweep mentioned in the previous post on May 4, 2020:

Step Index:    1      2      3      4      5      6      7      8      9
fOut:       5140   5160   5180   5200   5220   5200   5180   5160   5140 MHz
N:           257    258    259    260    261    260    259    258    257    
VCO_SEL:       4      4      4      4      4      4      4      4      4      
VCO_CAPCTRL:  39     36     33     29     26     29     33     36     39     
VCO_DACISET: 178    179    180    174    175    174    180    179    178    
Lock Time:    16     17     40     17     17     17     17     17     17 us

The sweeps repeatedly go from step index 1 to 9 in the above table. For each frequency step, the following registers are written in that order: 75, 45, 37, 36, 34, 20, 19, 16, 8. There are no large steps neither in VCO_CAPCTRL nor in VCO_DACISET.

Lock time is measured from the beginning of SPI write (9 registers, 30 MHz) to LD out going high at the MUXOUT pin. The long lock time occurs only when N changes from 258 to 259 (step 2 to 3), but not when it changes from 259 to 258, as already mentioned earlier.

Previously the long lock time when N changed from 258 to 259 was 50 us. This was with PFD_DLY_SEL set to 3. I corrected this to 1 (integer mode, VCO frequency > 4000 MHz), which resulted in an improvement of 10 us.

I also tried more complex sweeps with up to 281 steps, N ranging from 160 to 318, and VCO_SEL from 1 to 6. When doing these sweeps in ascending order of N, lock time is 20 us at most, except at steps where VCO_SEL changes it is up to 25 us, and at the only step where N changes from 258 to 259 it is again 40 us.

Hi Websurfer,

I am afraid I cannot explain why the lock time is longer between step 2 and 3, there is no big change in VCO data.

If you can take a transient plot (freq vs time), it will help debug.