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LMK05318: A jitter cleaner using LMK05318 instead of LMK03328

Part Number: LMK05318
Other Parts Discussed in Thread: LMK03328

Hi all

Would you mind if we ask LMK05318?

Please advise us on our questions bellow.
We consider implementing a jitter cleaner using LMK05318 instead of LMK03328 which outputs the same frequency as its input.
The input frequencies are something between 25MHz to 500 MHz with granular of 1MHz.
The main objective of using LMK05318 is to implement PLL loop bandwidth as low as 1 or 10 Hz. 
We tried to simulate performance of LMK05318 using PLLatinumSim

<Question1>
Does the PLLatinumSim simulate a part of this device such as APLL1 and APLL2?

<Question2>
If so, can you let us know how to simulate entire devices including DPLL?
Because only DPLL may be able to realize loop bandwidth as low as 1 Hz.

<Question3>
Please also let us know how to implement 1 Hz loop bandwidth and expected phase noise performance under the condition of 148.5 MHz input and output.

Kind regards,

Hirotaka Matsumoto

  • Hi Hirotaka-san,

    The PLLatinum sim can simulate the APLL1 and APLL2 separately. The idea is to save the output phase noise of APLL1 and feed that as reference noise to APLL2. The DPLL cannot be simulated in PLLatinum sim as of now, but if the clock to be cleaned is injected into PRIREF or SECREF and the phase noise after DPLL loop bandwidth will be replaced by internal TDC noise and BAW VCO phase noise. So you can refer to figure 8 of datasheet for APLL1 output phase noise. APLL2 phase noise can be simulated in Ticspro.

    DPLL loop bandwidth can be easily set in Ticspro:

    Regards,
    Hao

  • Hao san

    Thank you for your reply.

    We would like to confirm follows;

    So you can refer to figure 8 of datasheet for APLL1 output phase noise.
    ->We would like to know how to simulate using PLLatinum sim in case of cascade connection with PLL1 and PLL2.
      20200430_LMK05318.pdf
      We simulated it using PLLatinum, however we could not understand how to insert PLL1's VCO1 noise to PLL2's Fosc.
      (Where should we insert VCO1's noise to realize custom setting?Or, PLLatinum could not realize customer setting of inserting noise??)
      Could you refer to the attachment file? 

    APLL2 phase noise can be simulated in Ticspro.
    ->It seems that TICSPRO doesn't have simulation function, is it typo of PLLatinum??

    Kind regards,

    Hirotaka Matsumoto

  • Hao san

    In relation to our last post, it seems that we could understand how to insert VCO's noise.
    We would like to confirm how to insert VCO's noise correctly.

    1. At OSC, PLL and VCO Noise data of PLLatinum, we choice Load data
    2. We select the offset data which is producted with .txt.

    <Question1>
    We have a question this format.
    We would like to insert following nose;
    Offset(kHz)  (dBc/Hz)
    100,-            -72.6
    1000,           -100.7
    10000,         -128.6
    100000,        -149.6
    1000000,      -158.7
    10000000,    -159.0

    So, We recognize that contents of .txt are follows;
    100,-72.6
    1000,-100.7
    10000,-128.6
    100000,-149.6
    1000000,-158.7
    10000000,-159.0
     <Offset in Hz> +delimiter+<Phase Noise in Dbc>+ CarriageReturn
    Is it correct?

    About <Question2> and <Question3>, could you refer to the attachment file?
    20200501_LMK05318_PLLatinum.pdf

    Kind regards,

    Hirotaka Matsumoto

  • Hao san

    If you have some update for our last update, could you let us know??

    Kind regards,

    Hirotaka Matsumoto

  • Hao san

    Could you let us know your circumstance?

    Kind regards,

    Hirotaka Matsumoto

  • Hi team

    Our last update is relation to PLLatinum application.
    So, should we make the new thread on E2E forum?

    Kind regards,

    Hirotaka Matsumoto

  • Matsumoto-san,

    Yes, this will work.

    Typically what I do is type in Excel and save as "Tab Delimited Text".  But also it recognizes other delimiters like CRLF and ",".

    Regards,

    Dean