Other Parts Discussed in Thread: LMK03328
Hi all
Would you mind if we ask LMK05318?
Please advise us on our questions bellow.
We consider implementing a jitter cleaner using LMK05318 instead of LMK03328 which outputs the same frequency as its input.
The input frequencies are something between 25MHz to 500 MHz with granular of 1MHz.
The main objective of using LMK05318 is to implement PLL loop bandwidth as low as 1 or 10 Hz.
We tried to simulate performance of LMK05318 using PLLatinumSim
<Question1>
Does the PLLatinumSim simulate a part of this device such as APLL1 and APLL2?
<Question2>
If so, can you let us know how to simulate entire devices including DPLL?
Because only DPLL may be able to realize loop bandwidth as low as 1 Hz.
<Question3>
Please also let us know how to implement 1 Hz loop bandwidth and expected phase noise performance under the condition of 148.5 MHz input and output.
Kind regards,
Hirotaka Matsumoto