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LMK03328: LMK03328

amnon pomerants
Intellectual 780 points
Part Number: LMK03328

Hi

I want to connect the LMK03328 to a clock distributor defined as 1.8V AC LVDS.

The connection is according to the distributor recommendation: a 100nF serial capacitor at the Pos and at the Neg LMK03328 pins, connected to a 100ohm termination between the Pos/ Neg of the receiver (the Clocks distributor) .

However, HyperLynx simulation shows bad SI both at Pre-layout and at Post Layout (the Neg signal looked OK and the Pos signal had several (!) levels which caused the differential signal to look very bad). 

I have tried two things:

1. Short the capacitors

2. Move the 100ohm resistor to the left of the serial capacitors

Both attempts ended with much better SI signals. 

Can the LMK03328 drive at all a receiver which is "AC LVDS" ?

Can you explain please the above?

How to proceed?

Thanks

Amnnon

  • 0
    TI__Expert 6140 points

    Hello Amnnon, 

    Yes LMK03328 can drive an AC LVDS receiver, I'm not sure what exactly is causing the problem you're seeing.. the n and p shouldn't be different for one and the 0.1 uF cap should be used. 

    Is there any difference / improvement if you use a single ended 50 ohm to ground termination as oppose to 100 ohm differential between n and p? 

    Thanks and regards, Amin

  • 0 in reply to Amin Eshraghi
    Intellectual 780 points

    Hello Amin

    Sorry, No  difference / improvement if I use a single ended 50 ohm to ground termination instead of the 100 ohm differential.

    I took the exact failed HyperLynx file and made only one change: replaced the LVDS_AC / LVDS_1.8V module with the HCSL_1.8V module and the signals turned to be just fine (Pos = Not Neg instead of the current POS = 0.5x Neg).

    I looks to me as an IBIS problem.

    Can you please double check the IBIS section of the AC-LVDS_1.8V of the POS pin?

    Thanks

    Amnon

  • 0 in reply to amnon pomerants
    TI__Expert 6140 points

    Hi Amnon, 

    Apologies this is taking longer than expected, but we're looking into this and we'll let you know. This the same issue as this thread: 

    http://e2e.ti.com/support/clock-and-timing/f/48/p/902706/3341334#3341334

    Correct? 

    If so I would like to close one and continue the conversation in just one of the. 

    Also, if you would like to share your schematic file that way we can simulate that exact model and see what's happening. You could go ahead and share it in the other thread. 

    Thanks and regards,

    Amin