LMK04826: LMK04826B lock time simulation method

Hi JH,

At this time, we do not have a tool to simulate lock time behavior for LMK04826. In the future we have plans to add this capability to PLLatinum Sim software.

A general rule of thumb is that lock time can be approximated by 4 / loop bandwidth. PLLatinum Sim can be used to estimate the effect of increasing the charge pump gain on the loop bandwidth, and in this sense can provide some general lock time information. Increasing charge pump gain, while leaving all other settings constant, will tend to increase loop bandwidth; so we would expect lock time to be reduced by a comparable amount. As an example, I tested the default settings for LMK04826 PLL1 with 0.45mA and 0.85mA charge pump, and got around 100Hz and 190Hz loop bandwidth respectively; in the 0.45mA charge pump case, I would expect base lock time to be around 4/100Hz = 40ms, and in the 0.85mA charge pump case, I would expect base lock time to be around 4/190Hz = 21ms.

Especially for PLL1, there are some considerations for cases with high phase detector frequency and low loop bandwidth due to cycle slip. As a general rule, (Fpd / loop bandwidth) < (5 / frequency change %). For example, using a VCXO with ±2000 ppm adjustment range, the maximum expected frequency change expressed as a percentage is |1 - (f + 2000ppm)/(f - 2000ppm)| = about 0.4%; so the ratio of Fpd to loop bandwidth should be no greater than 5/0.004 = 1250 before cycle slipping begins to affect lock time. With a loop bandwidth of 100Hz and Fpd = 1.024MHz, the ratio is about 10240, so cycle slip would have some significant impact. The approximate lock time multiplier is (2/3) * (Fpd / loop bandwidth) * frequency change % / 5. Taking the 0.45mA charge pump example from above as a base rate, and with the Fpd and loop bandwidth suggested, I predict the impact of cycle slip will act as a multiplying factor of (2/3) * (10240) * 0.004 / 5 = about 5.46 to the base rate. So the cycle slip-adjusted lock time would be (4/100Hz) * 5.46 = about 218ms. Likewise, in the 0.85mA charge pump case, the new lock time would be (4/190Hz) * 5.46 = about 115ms.

There are some other possible effects due to various system nonlinearities such as charge pump mismatch, leakage current, or capacitor dielectric memory effects in the loop filter, but their overall contribution will be minor compared to loop bandwidth and cycle slip effects. For more information about lock time, consider reviewing PLL Performance, Simulation, and Design by my colleague Dean Banerjee, in which lock time and many other PLL effects are explored in detail. The lock time specifics are discussed in the sections on transient response.

Regards,