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CDCE62005 SPI_MiSO open drain?

Jan Schirok
Prodigy 30 points
Other Parts Discussed in Thread: CDCE62005, CDCE72010, CDCE62002

Hi,

we're using the above TI clock manager CDCE62005 in a project (it also applies to CDCE72010).

After reading the CDCE62002/CDCE62005 SPI related app note I found the MISO line being declared as "open-drain".

This would imply, that the pin has to be pulled up externally via resistor in order to see a high level.

In the mentioned App-Note, the oscilloscope plots for the MISO line indicate a bidirectional behaviour, rather than a open-drain behaviour. (Charging-curve when LE is going high, but "normal" edges on MISO otherwise).

Which is correct? Is the pin open-drain or bidirectional (high impedance when LE is high, actively driving otherwise)?

Best regards,

Jan

 

  • 0
    Prodigy 30 points

    Hi again,

     

    I checked the issue with a CDCE72010. It is not open-drain but, as expected (or hoped), bidirectional. This is the standard behaviour for SPI-based devices.

    When LE is high, the output (MISO) is tri-state, when low (chip selected), it is driven actively.

    The documentation of the CDCE72010/CDCE62005 should be updated, because "open-drain" is ambiguous in this context.

     

    Best regards,

    Jan