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LMK04832: LMK04832 PLLatinum Sim Question

usethewrench
Prodigy 140 points
Part Number: LMK04832

In order to analyze the LMK04832 overall phase noise performance for dual loop mode, I first analyze PLL1, and then export trace, and then use that trace as the source when analyzing PLL2.  My question is regarding analysis of PLL1.

1. When analyzing PLL1 with the intent of using it as an input to PLL2, and when planning to have the VCXO frequency of PLL1 be the input frequency to PLL2, is it correct to uncheck "Enable Output/Divider Noise" under other noise sources? 

Thanks

  • 0
    TI__Mastermind 33760 points

    Hi usethewrench,

    "Enable Output/Divider Noise" for PLL1 refers to the OSCout buffer. PLL2 analysis already takes the OSCin buffer noise floor into account with the PLL flicker/FOM. In other words, "Enable Output/Divider Noise" should not be checked when saving the PLL1 output for import to PLL2's OSC source noise.

    Regards,