LMK04832: SDCLK1 and DCLK8 are "Not" Phase Aligned after I SYNC the Dividers ["Off" by 1 VCO Clock]

So here’s my Setup

1. I Set Up Clock Group1 as follows:

// Clock Group 1 (DCLK0 = Powered Down, SDCLK1 = 320MHz)

Write 0x0100, 0x0A; DCLK0_1_DIV = 10 [3200MHz/10 = 320MHz]

Write 0x0101, 0x08; DCLK0_1_DDLY = 8

Write 0x0102, 0x00; CLK0_1_PD = 0, ODL = 0, IDL = 0, DDLY0_1_PD = 0, DDLY[9:8] = 0, DIV[9:8] = 0

Write 0x0103, 0x44; DCLK0_1_HS = 0, DCLK0_1_POL = 0, DCLK0_1_DCC = 1, DCLK0_BYP = 0, CLKout0_1_PD = 0, CLKout0_SRC_MUX = 0 {Device}, DCLK0_1_HSg_PD = 1

Write 0x0104, 0x00; SCLK0_1_HS = 0, SCLK0_1_POL = 0, SCLK0_1_DIS_MODE = 0, SCLK0_1_PD = 0, CLKout1_SRC_MUX = 0 [Device]

Write 0x0105, 0x00; No Analog Delay, Disable Analog Delay

Write 0x0106, 0x00; SCLK0_1_DDLY = 0

Write 0x0107, 0x40; SDCLK1 = LVPECL16, DCLK0 = Powered Down

1. I Set Up Clock Group5 as follows:

// Clock Group 5 (DCLK8 = 640MHz, SDCLK9 = SYSREF)

Write 0x0120, 0x05; DCLK8_9_DIV = 5 [3200MHz/5 = 640MHz]

Write 0x0121, 0x08; DCLK8_9_DDLY = 8

Write 0x0122, 0x00; CLK8_9_PD = 0, ODL = 0, IDL = 0, DDL8_9_PD = 0, DDL[9:8] = 0, DIV[9:8] = 0

Write 0x0123, 0x44; DCLK8_9_HS = 0, DCLK8_9_POL = 0, DCLK8_9_DCC = 1, DCLK8_BYP = 0, CLKout8_9_PD = 0, CLKout8_SRC_MUX = 0 {Device}, DCLK8_9_HSg_PD = 1

Write 0x0124, 0x24; SCLK8_9_HS = 0, SCLK8_9_POL = 0, SCLK8_9_DIS_MODE = 1, SCLK6_7_PD = 0, CLKout9_SRC_MUX = 1 [SYSREF]

Write 0x0125, 0x00; No Analog Delay, Disable Analog Delay

Write 0x0126, 0x00; SCLK8_9_DDLY = 0

Write 0x0127, 0x11; SDCLK9 = LVDS, DCLK8 = LVDS

1. When I “SYNC” the Output Dividers, I see that SDCLK1 [320MHz] is “Not” Phase Aligned with DCLK8 [640MHz]…….with DCLK0_1_DDLY = 8 and DCLK8_9_DDLY = 8

2. On PDF Page 52, it states that Depending on the DCLK divide value, there may be an adjustment in phase delay required. Table 18 illustrate the impact of different divide values on the final digital delay.

3. For Clock Group1, there is a Divide by 10 [DCLK0 = 3200MHz/10 = 320MHz]. Table 18 shows that +0 [VCOs] is incurred. Table 19 shows with DCLK0_1_DDLY = 8, the “Actual” DDLY will be 8.

4. For Clock Group5, there is a Divide by 5 [DCLK8 = 3200MHz/5 = 640MHz]. Table 18 shows that an additional +3 [VCOs] is incurred. Table 19 shows with DCLK8_9_DDLY = 8, the “Actual” DDLY will be 11.

5. I then go back and “Change” DCLK0_1_DDLY to “11” to “Align” the Phase of SDCLK1 with DCLK8.

6. I then “SYNC” the Output Dividers again!

7. I expected to see SDCLK1 [320MHz, LVPECL, Divide by 10, DCLK0_1_DDLY = 11] “Phase” Aligned with DCLK8 [640MHz, LVDS, Divide by 5, DCLK8_9_DDLY = 8]…….however……..I see a (1) VCO Clock Difference in Phase???

8. It appears that I need to set DCLK0_1_DDLY to “10” as opposed to “11”

9. In other words……the Digital Delay Adjustment listed in Table 18 for Divide by 5 should be +2 and “Not” +3!

10. Can you “Verify” that +2 is the “Correct” Answer?

11. PDF Page 12 lists Clock Skew for (4) Different Cases

    1. CLKoutX to CLKoutX [Any even CLKoutX, Same Format Device Clock]; 60ps Typ.

    2. CLKoutX to CLKoutY [Even to even or odd to odd, Same Format Device Clock]; 60ps Typ.

    3. CLKoutX or Y to any CLKoutX or Y [Any output, Same Format Device Clock]; 100ps Typ.

    4. CLKoutX to CLKoutY [Same Pair of Device Clocks, Same Format]; 35ps Type.

12. My Use case is SDCLK1 to DCLK8 which doesn’t appear to be “Any” of the (4) Skew Examples listed. I did note that for the (4) Examples Listed, the Typical Range is 35ps to 100ps…….but I am measuring a Phase Difference of approximately 320ps [1 VCO = 1/3200MHz = 312.5ps] which appears to be a “VCO” Difference as opposed to a “Pin-To-Pin” Skew Error.