LMK04610: Zero Delay Mode and Manual Sync

DanP

Part Number: LMK04610

Hi,

I am doing an evaluation of LMK04610 using LMK04610EVM and have troubles related to Sync functionality which in turn causing PLL2 to loose lock. Attached TICS Pro file. PLL2_FBDIV_MUXSEL is configured to take feedback from OUTCH5.

In my setup i am using 325MHz reference clock fed to clock input 1. PLL1 is bypassed. The sequence i am following is:

1. Toggle RESETN mark in User Control tab in TICS Pro

2. Generic -> Device Start

3. Write all registers from top menu

At this point i see correct clocks on device output

Checking PLL2 lock in Generic->Update and PLL2 appear to be locked

The first unexpected observation I see is that the relationship between two different outputs CH9 and CH5 is changing from every time I do the reset. according to Figure 51, most right branch of power up seems like SYNC release is part of the process. Thus it's not clear to me why the clocks don't maintain timing relationship

Next, to try to align the outputs I am using toggle sync manually using the top menu in TICS Pro. I can observe outputs realign to same place every time. and I still see good outputs.

However when I go to generic tab -> Update I see that PLL2_LCK_DET bit went to 0. the only way to bring it back to lock is to follow the process I described with Reset without a good clock output alignment.

Could you please help me to understand whats going on?

Also while experimenting i noticed that if i disable SYNC_EN for CH5, seems like PLL2 doesnt loose lock when manually SYNCed. This raises the question if its possible to have CH5 used as feedback and being used externally when all outputs need to be SYNCed.

Thank you very much

lmk04610 pll2 zdm for TI.tcs

over 5 years ago

0 Derek Payne over 5 years ago

TI__Mastermind 33580 points

Hi Dan,

First, the recommended programming sequence has your steps 2 and 3 reversed - you should write all registers, then do Generic -> Device Start. This may explain the variation in startup phase you have observed.

Also, note in the programming sequence that RESET_PLL2_DLD must be set (0xAD=0x03, wait 20ms, 0xAD=0x00) after programming. This also applies to output divider synchronization when the divider used for zero-delay feedback is reset.

Regards,

0 DanP over 5 years ago in reply to Derek Payne

Prodigy 80 points

Hi Derek,

Thank you for your response. I tested the proposed correction of programming flow to first write all registers and then start the device. it indeed helped and i can see CH5 wakes up in sync with rest of outputs. The pll is locked as well at the start.

This solves my problem. However just to understand better the limitations. if i apply manual toggle of sync signal the PLL2_LCK_DET is de-asserted. Is it correct behaviour and if yes if there is any way to relock the PLL besides doing full HW reset through reset pin and repeat programming sequence?

Thanks again

Dan

0 Derek Payne over 5 years ago in reply to DanP

TI__Mastermind 33580 points

Hi Dan,

PLL2_LCK_DET should deassert when the zero-delay output divider is reset, since the PLL will lose lock. However, due to a "quirk" of the digital circuitry controlling the state machine used for lock detect, SYNC, SYSREF, etc, losing the N-divider clock temporarily when in zero-delay mode seems to put the state machine in a state from which the device does not recover without a reset. There is a register, PORCLKAFTERLOCK (0x12[0]) which can be used to force the internal RC-oscillator state machine clock to persist after PLL2 acquires lock; setting PORCLKAFTERLOCK=1 appears to allow the PLL2_LCK_DET circuitry to continue operating correctly through SYNCing the zero-delay feedback output divider.

Regards,

0 DanP over 5 years ago in reply to Derek Payne

Prodigy 80 points

Thank you very much

Dan

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LMK04610: Zero Delay Mode and Manual Sync