LMX2595: LMX2595

Hi,

1)  For the inductors and capacitors, not sure exactly which ones you mean.

For the Vcc pins, these values are not so critical and this is more of a reflection of what we did on our evaluation boards.  For some of the others, like Vbias and others, this has more of an impact.  For the pull-ups on RFout, then this is critical.

2) For the AC coupling value, you want it to be low impedance at the frequency of interest.  For this EVM, we have some high performance RF capacitors that are actually good for a broadband match.  On the RF  output, the capacitor might seem large for higher frequencies, but don't be deceived, these are high performance RF capacitors.

3&4)   Lock time is application specific and depends on a few things, like the loop bandwidth.  Our PLLatinum Sim tool can simulate this.

5)  For output power, the input reference power has minimal to no impact.  On our EVM, understand that this is not optimal for output power as the traces are longer;  by doing single-ended routing, you can get more power.   Also, for the datasheet, understand that board losses have been subtracted away.  Figure 25 shows that we can get -3 dBm at 20 GHz woth OUTx_PWR=20 setting.

6)  I think that 10 mils is better, but this depends on the dielectric and thickness to first layer.   For us, the availability of high frequency RF connector was one consideration as to what trace width to design our board around.

7)  The 256 kHz loop bandwidth was targeting optimal jitter for phase detector frequency of 200 MHz.  However, if you want faster lock time, design wider.  Or if you are in fractional use case, consider decreasing this.  I would encourage you to try our PLLatinum Sim Software.

REgards,

Dean

Hi

1)  I don't follow this at all.  0.1 uF at 10 MHz is 1/(6.283*10e6*1e-7) = 0.16 ohm, which is plenty low enough.   The OSCin and RFout pins should not be running in the kHz range.  So for the OSCin pin, if you have 100 MHz, 0.1 uF is 0.016 ohms, which should be low enough and fine.

On the RF outputs, theoretically higher capacitance is better, but at some point, the self-resonant frequency becomes an issue, but this is more something about the capacitor, not our part.  We use on our EVM capacitors with very high self-resonant frequency and good RF performance,   But if you want to use cheaper capacitors, maybe a fair balance between theoretical low impedance and self-resonant frequency.  would be choose it such that the impedance is on the order of 1 ohm.

2) Our EVM supports many features, but if you did a two sided board with both sides assembled, I'm pretty sure you could cram it into a space under 1.5 x 1.5 inch.  You can use 0402 components

3)  PLLatinum Sim does do lock time simulation.  Click on the "Lock Time Tab".  It should be there with the other tabs.  The lock time is dominated by the VCO calibration time, so loop bandwidth is not the only impact, but for just the analog settle time, a coarse rule of thumb is 4/LoopBandwidth.

4)  For the input reference, there are many choices.  A wenzel oscillator has the ultimate phase noise and really good frequency accuracy and stability.  TI makes the LMK061xx family of crystal oscillators.  There are a huge variety of choices.  PLLatinum Sim allows you to import the noise of the reference oscillator.  If you don't use something ultra-low noise, like the wenzel, the input reference noise will degrade the output phase noise and jitter, but your system requirments dictate what this should be.

Regards,

Dean